maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU: Remove AMDIL.fraction intrinsic 

llvm-svn: 258347
This commit is contained in:
Matt Arsenault 2016-01-20 21:05:49 +00:00
parent 7cccd2672e
commit 15fbe49daf
5 changed files with 4 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td
View File

@ -71,7 +71,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
// Legacy names for compatibility.
let TargetPrefix = "AMDIL", isTarget = 1 in {
def int_AMDIL_fraction : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_AMDIL_clamp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
def int_AMDIL_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
}

1
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
View File

@ -853,7 +853,6 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_fract:
case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
}
// break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())

3
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -1360,8 +1360,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(2),
Op.getOperand(3));
case AMDGPUIntrinsic::AMDGPU_fract:
case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
case AMDGPUIntrinsic::AMDGPU_fract: // Legacy name.
return DAG.getNode(ISD::FSUB, DL, VT, Op.getOperand(1),
DAG.getNode(ISD::FFLOOR, DL, VT, Op.getOperand(1)));
case AMDGPUIntrinsic::SI_fs_constant: {

16
llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll
View File

@ -6,9 +6,6 @@
declare float @llvm.fabs.f32(float %Val)
declare float @llvm.AMDGPU.fract.f32(float) nounwind readnone
; Legacy name
declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone
; FUNC-LABEL: {{^}}fract_f32:
; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
@ -22,19 +19,6 @@ define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounw
ret void
}
; FUNC-LABEL: {{^}}fract_f32_legacy_amdil:
; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]]
; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]]
; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]]
; GCN: buffer_store_dword [[RESULT]]
; EG: FRACT
define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind {
%val = load float, float addrspace(1)* %src, align 4
%fract = call float @llvm.AMDIL.fraction.f32(float %val) nounwind readnone
store float %fract, float addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}fract_f32_neg:
; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]]
; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -[[INPUT:v[0-9]+]]

6
llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
View File

@ -256,7 +256,7 @@ ELSE2584: ; preds = %IF2565
ENDIF2582: ; preds = %ELSE2584, %IF2565
%213 = fadd float %1, undef
%214 = fadd float 0.000000e+00, %213
%215 = call float @llvm.AMDIL.fraction.(float %214)
%215 = call float @llvm.AMDGPU.fract.f32(float %214)
br i1 undef, label %IF2589, label %ELSE2590
IF2589: ; preds = %ENDIF2582
@ -479,8 +479,8 @@ ELSE2824: ; preds = %ELSE2821
; Function Attrs: nounwind readnone
declare float @llvm.SI.load.const(<16 x i8>, i32) #1
; Function Attrs: readnone
declare float @llvm.AMDIL.fraction.(float) #2
; Function Attrs: nounwind readnone
declare float @llvm.AMDGPU.fract.f32(float) #1
; Function Attrs: nounwind readnone
declare float @llvm.sqrt.f32(float) #1