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Elimiante SP and FP, which weren't members of the IntRegs register class 

llvm-svn: 24844
This commit is contained in:
Chris Lattner 2005-12-19 00:06:52 +00:00
parent c06da626b4
commit 15bd5ea92f
4 changed files with 13 additions and 29 deletions
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2
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
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@ -450,7 +450,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
if (ValToStore.Val) { if (ValToStore.Val) {
if (!StackPtr.Val) { if (!StackPtr.Val) {
StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32); StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL); NullSV = DAG.getSrcValue(NULL);
} }
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());

18
llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
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@ -879,7 +879,7 @@ void V8ISel::visitCallInst(CallInst &I) {
"About to dereference past end of OutgoingArgRegs"); "About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg); BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else { } else {
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (ArgReg); .addReg (ArgReg);
} }
ArgOffset += 4; ArgOffset += 4;
@ -894,7 +894,7 @@ void V8ISel::visitCallInst(CallInst &I) {
"About to dereference past end of OutgoingArgRegs"); "About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0); BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
} else { } else {
BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STFri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (ArgReg); .addReg (ArgReg);
} }
ArgOffset += 4; ArgOffset += 4;
@ -913,7 +913,7 @@ void V8ISel::visitCallInst(CallInst &I) {
} else { } else {
unsigned TempReg = makeAnotherReg (Type::IntTy); unsigned TempReg = makeAnotherReg (Type::IntTy);
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0); BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (TempReg); .addReg (TempReg);
} }
ArgOffset += 4; ArgOffset += 4;
@ -924,7 +924,7 @@ void V8ISel::visitCallInst(CallInst &I) {
} else { } else {
unsigned TempReg = makeAnotherReg (Type::IntTy); unsigned TempReg = makeAnotherReg (Type::IntTy);
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4); BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (TempReg); .addReg (TempReg);
} }
ArgOffset += 4; ArgOffset += 4;
@ -935,7 +935,7 @@ void V8ISel::visitCallInst(CallInst &I) {
"About to dereference past end of OutgoingArgRegs"); "About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg); BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else { } else {
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (ArgReg); .addReg (ArgReg);
} }
ArgOffset += 4; ArgOffset += 4;
@ -945,7 +945,7 @@ void V8ISel::visitCallInst(CallInst &I) {
"About to dereference past end of OutgoingArgRegs"); "About to dereference past end of OutgoingArgRegs");
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1); BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
} else { } else {
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset) BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
.addReg (ArgReg+1); .addReg (ArgReg+1);
} }
ArgOffset += 4; ArgOffset += 4;
@ -1708,11 +1708,11 @@ void V8ISel::visitAllocaInst(AllocaInst &I) {
BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8); BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
// Subtract size from stack pointer, thereby allocating some space. // Subtract size from stack pointer, thereby allocating some space.
BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg); BuildMI (BB, V8::SUBrr, 2, V8::O6).addReg (V8::O6).addReg (StackAdjReg);
// Put a pointer to the space into the result register, by copying // Put a pointer to the space into the result register, by copying
// the stack pointer. // the stack pointer.
BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96); BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::O6).addSImm (96);
// Inform the Frame Information that we have just allocated a variable-sized // Inform the Frame Information that we have just allocated a variable-sized
// object. // object.
@ -1755,7 +1755,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
// Add the VarArgsOffset to the frame pointer, and copy it to the result. // Add the VarArgsOffset to the frame pointer, and copy it to the result.
unsigned DestReg = getReg (CI.getOperand(1)); unsigned DestReg = getReg (CI.getOperand(1));
unsigned Tmp = makeAnotherReg(Type::IntTy); unsigned Tmp = makeAnotherReg(Type::IntTy);
BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset); BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::I6).addSImm (VarArgsOffset);
BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp); BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
return; return;
} }

19
llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
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@ -25,19 +25,6 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN, : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
V8::ADJCALLSTACKUP) {} V8::ADJCALLSTACKUP) {}
static const TargetRegisterClass *getClass(unsigned SrcReg) {
if (V8::IntRegsRegisterClass->contains(SrcReg))
return V8::IntRegsRegisterClass;
else if (V8::FPRegsRegisterClass->contains(SrcReg))
return V8::FPRegsRegisterClass;
else if (V8::DFPRegsRegisterClass->contains(SrcReg))
return V8::DFPRegsRegisterClass;
else {
std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
abort ();
}
}
void SparcV8RegisterInfo:: void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx, unsigned SrcReg, int FrameIdx,
@ -93,7 +80,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
int size = MI.getOperand (0).getImmedValue (); int size = MI.getOperand (0).getImmedValue ();
if (MI.getOpcode () == V8::ADJCALLSTACKDOWN) if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
size = -size; size = -size;
BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size); BuildMI (MBB, I, V8::ADDri, 2, V8::O6).addReg (V8::O6).addSImm (size);
MBB.erase (I); MBB.erase (I);
} }
@ -109,7 +96,7 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
int FrameIndex = MI.getOperand(i).getFrameIndex(); int FrameIndex = MI.getOperand(i).getFrameIndex();
// Replace frame index with a frame pointer reference // Replace frame index with a frame pointer reference
MI.SetMachineOperandReg (i, V8::FP); MI.SetMachineOperandReg (i, V8::I6);
// Addressable stack objects are accessed using neg. offsets from %fp // Addressable stack objects are accessed using neg. offsets from %fp
MachineFunction &MF = *MI.getParent()->getParent(); MachineFunction &MF = *MI.getParent()->getParent();
@ -141,7 +128,7 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
// is required by the ABI. // is required by the ABI.
NumBytes = (NumBytes + 7) & ~7; NumBytes = (NumBytes + 7) & ~7;
BuildMI(MBB, MBB.begin(), V8::SAVEri, 2, BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
V8::SP).addImm(-NumBytes).addReg(V8::SP); V8::O6).addImm(-NumBytes).addReg(V8::O6);
} }
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,

3
llvm/lib/Target/SparcV8/SparcV8RegisterInfo.td
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@ -45,9 +45,6 @@ def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">;
def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">; def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">;
def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">; def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">;
// Standard register aliases
def SP : Ri<14, "SP">; def FP : Ri<30, "FP">;
// Floating-point registers // Floating-point registers
def F0 : Rf< 0, "F0">; def F1 : Rf< 1, "F1">; def F2 : Rf< 2, "F2">; def F0 : Rf< 0, "F0">; def F1 : Rf< 1, "F1">; def F2 : Rf< 2, "F2">;
def F3 : Rf< 3, "F3">; def F4 : Rf< 4, "F4">; def F5 : Rf< 5, "F5">; def F3 : Rf< 3, "F3">; def F4 : Rf< 4, "F4">; def F5 : Rf< 5, "F5">;