forked from OSchip/llvm-project
Elimiante SP and FP, which weren't members of the IntRegs register class
llvm-svn: 24844
This commit is contained in:
parent
c06da626b4
commit
15bd5ea92f
llvm/lib/Target/SparcV8
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@ -450,7 +450,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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if (ValToStore.Val) {
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if (!StackPtr.Val) {
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StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::SP, MVT::i32);
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StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
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NullSV = DAG.getSrcValue(NULL);
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}
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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@ -879,7 +879,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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} else {
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (ArgReg);
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}
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ArgOffset += 4;
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@ -894,7 +894,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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} else {
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BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STFri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (ArgReg);
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}
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ArgOffset += 4;
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@ -913,7 +913,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (TempReg);
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}
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ArgOffset += 4;
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@ -924,7 +924,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (TempReg);
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}
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ArgOffset += 4;
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@ -935,7 +935,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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} else {
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (ArgReg);
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}
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ArgOffset += 4;
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@ -945,7 +945,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
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} else {
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::O6).addSImm (ArgOffset)
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.addReg (ArgReg+1);
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}
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ArgOffset += 4;
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@ -1708,11 +1708,11 @@ void V8ISel::visitAllocaInst(AllocaInst &I) {
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BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
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// Subtract size from stack pointer, thereby allocating some space.
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BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
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BuildMI (BB, V8::SUBrr, 2, V8::O6).addReg (V8::O6).addReg (StackAdjReg);
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// Put a pointer to the space into the result register, by copying
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// the stack pointer.
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BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
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BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::O6).addSImm (96);
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// Inform the Frame Information that we have just allocated a variable-sized
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// object.
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@ -1755,7 +1755,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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// Add the VarArgsOffset to the frame pointer, and copy it to the result.
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unsigned DestReg = getReg (CI.getOperand(1));
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unsigned Tmp = makeAnotherReg(Type::IntTy);
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BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
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BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::I6).addSImm (VarArgsOffset);
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BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
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return;
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}
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@ -25,19 +25,6 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
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: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
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V8::ADJCALLSTACKUP) {}
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static const TargetRegisterClass *getClass(unsigned SrcReg) {
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if (V8::IntRegsRegisterClass->contains(SrcReg))
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return V8::IntRegsRegisterClass;
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else if (V8::FPRegsRegisterClass->contains(SrcReg))
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return V8::FPRegsRegisterClass;
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else if (V8::DFPRegsRegisterClass->contains(SrcReg))
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return V8::DFPRegsRegisterClass;
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else {
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std::cerr << "Error: register of unknown class found: " << SrcReg << "\n";
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abort ();
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}
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}
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void SparcV8RegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FrameIdx,
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@ -93,7 +80,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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int size = MI.getOperand (0).getImmedValue ();
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if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
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size = -size;
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BuildMI (MBB, I, V8::ADDri, 2, V8::SP).addReg (V8::SP).addSImm (size);
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BuildMI (MBB, I, V8::ADDri, 2, V8::O6).addReg (V8::O6).addSImm (size);
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MBB.erase (I);
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}
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@ -109,7 +96,7 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace frame index with a frame pointer reference
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MI.SetMachineOperandReg (i, V8::FP);
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MI.SetMachineOperandReg (i, V8::I6);
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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@ -141,7 +128,7 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
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// is required by the ABI.
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NumBytes = (NumBytes + 7) & ~7;
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BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
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V8::SP).addImm(-NumBytes).addReg(V8::SP);
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V8::O6).addImm(-NumBytes).addReg(V8::O6);
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}
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void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
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@ -45,9 +45,6 @@ def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">;
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def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">;
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def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">;
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// Standard register aliases
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def SP : Ri<14, "SP">; def FP : Ri<30, "FP">;
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// Floating-point registers
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def F0 : Rf< 0, "F0">; def F1 : Rf< 1, "F1">; def F2 : Rf< 2, "F2">;
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def F3 : Rf< 3, "F3">; def F4 : Rf< 4, "F4">; def F5 : Rf< 5, "F5">;
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