forked from OSchip/llvm-project
[X86] Enable the use of movlps for i64 atomic load on 32-bit targets with sse1.
Still a little room for improvement by using movlps to store to the stack temporary needed to move data out of the xmm register after the load.
This commit is contained in:
Craig Topper
parent
2a10f8019d
commit
15b6aa7448
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@ -27544,7 +27544,7 @@ X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
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LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat);
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if (MemType->getPrimitiveSizeInBits() == 64 && !Subtarget.is64Bit() &&
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!Subtarget.useSoftFloat() && !NoImplicitFloatOps &&
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(Subtarget.hasSSE2() || Subtarget.hasX87()))
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(Subtarget.hasSSE1() || Subtarget.hasX87()))
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return AtomicExpansionKind::None;
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return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
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@ -29667,15 +29667,27 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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Attribute::NoImplicitFloat);
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if (!Subtarget.useSoftFloat() && !NoImplicitFloatOps) {
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auto *Node = cast<AtomicSDNode>(N);
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if (Subtarget.hasSSE2()) {
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// Use a VZEXT_LOAD which will be selected as MOVQ. Then extract the
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// lower 64-bits.
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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if (Subtarget.hasSSE1()) {
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// Use a VZEXT_LOAD which will be selected as MOVQ or XORPS+MOVLPS.
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// Then extract the lower 64-bits.
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MVT LdVT = Subtarget.hasSSE2() ? MVT::v2i64 : MVT::v4f32;
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SDVTList Tys = DAG.getVTList(LdVT, MVT::Other);
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SDValue Ops[] = { Node->getChain(), Node->getBasePtr() };
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SDValue Ld = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
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MVT::i64, Node->getMemOperand());
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SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
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if (Subtarget.hasSSE2()) {
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SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Ld,
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DAG.getIntPtrConstant(0, dl));
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Results.push_back(Res);
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Results.push_back(Ld.getValue(1));
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return;
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}
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// We use an alternative sequence for SSE1 that extracts as v2f32 and
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// then casts to i64. This avoids a 128-bit stack temporary being
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// created by type legalization if we were to cast v4f32->v2i64.
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SDValue Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2f32, Ld,
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DAG.getIntPtrConstant(0, dl));
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Res = DAG.getBitcast(MVT::i64, Res);
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Results.push_back(Res);
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Results.push_back(Ld.getValue(1));
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return;
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@ -107,18 +107,17 @@ define void @fadd_64r(double* %loc, double %val) nounwind {
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; X86-SSE1-NEXT: pushl %ebp
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: subl $16, %esp
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; X86-SSE1-NEXT: movl 8(%ebp), %eax
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; X86-SSE1-NEXT: fildll (%eax)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-SSE1-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %ecx, (%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: xorps %xmm1, %xmm1
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; X86-SSE1-NEXT: movss %xmm1, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fldl (%esp)
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; X86-SSE1-NEXT: faddl 12(%ebp)
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; X86-SSE1-NEXT: fstpl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movlps %xmm0, (%eax)
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; X86-SSE1-NEXT: movl %ebp, %esp
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@ -274,17 +273,16 @@ define void @fadd_64g() nounwind {
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; X86-SSE1-NEXT: pushl %ebp
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: fildll glob64
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, (%esp)
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; X86-SSE1-NEXT: subl $16, %esp
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: xorps %xmm1, %xmm1
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; X86-SSE1-NEXT: movss %xmm1, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fld1
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; X86-SSE1-NEXT: faddl (%esp)
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; X86-SSE1-NEXT: fstpl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movlps %xmm0, glob64
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; X86-SSE1-NEXT: movl %ebp, %esp
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@ -438,17 +436,16 @@ define void @fadd_64imm() nounwind {
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; X86-SSE1-NEXT: pushl %ebp
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: fildll -559038737
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, (%esp)
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; X86-SSE1-NEXT: subl $16, %esp
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: xorps %xmm1, %xmm1
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; X86-SSE1-NEXT: movss %xmm1, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fld1
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; X86-SSE1-NEXT: faddl (%esp)
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; X86-SSE1-NEXT: fstpl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movlps %xmm0, -559038737
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; X86-SSE1-NEXT: movl %ebp, %esp
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@ -608,17 +605,16 @@ define void @fadd_64stack() nounwind {
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; X86-SSE1-NEXT: pushl %ebp
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $32, %esp
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; X86-SSE1-NEXT: fildll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, (%esp)
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; X86-SSE1-NEXT: subl $24, %esp
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: xorps %xmm1, %xmm1
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; X86-SSE1-NEXT: movss %xmm1, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fld1
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; X86-SSE1-NEXT: faddl (%esp)
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; X86-SSE1-NEXT: fstpl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %ebp, %esp
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@ -712,25 +708,22 @@ define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) nounwind {
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; X86-SSE1: # %bb.0: # %bb
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; X86-SSE1-NEXT: pushl %ebp
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; X86-SSE1-NEXT: movl %esp, %ebp
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; X86-SSE1-NEXT: pushl %esi
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; X86-SSE1-NEXT: andl $-8, %esp
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; X86-SSE1-NEXT: subl $32, %esp
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; X86-SSE1-NEXT: subl $16, %esp
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; X86-SSE1-NEXT: movl 20(%ebp), %eax
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; X86-SSE1-NEXT: movl 8(%ebp), %ecx
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; X86-SSE1-NEXT: fildll (%ecx,%eax,8)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-SSE1-NEXT: movl %esi, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %edx, (%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: xorps %xmm1, %xmm1
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; X86-SSE1-NEXT: movss %xmm1, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm1, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fldl (%esp)
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; X86-SSE1-NEXT: faddl 12(%ebp)
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; X86-SSE1-NEXT: fstpl {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movlps %xmm0, (%ecx,%eax,8)
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; X86-SSE1-NEXT: leal -4(%ebp), %esp
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; X86-SSE1-NEXT: popl %esi
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; X86-SSE1-NEXT: movl %ebp, %esp
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; X86-SSE1-NEXT: popl %ebp
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; X86-SSE1-NEXT: retl
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;
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@ -272,17 +272,16 @@ define float @load_float(float* %fptr) {
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define double @load_double(double* %fptr) {
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; X86-SSE1-LABEL: load_double:
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; X86-SSE1: # %bb.0:
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; X86-SSE1-NEXT: subl $20, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 24
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; X86-SSE1-NEXT: subl $12, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: fildll (%eax)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, (%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movss %xmm0, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fldl (%esp)
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; X86-SSE1-NEXT: addl $20, %esp
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; X86-SSE1-NEXT: addl $12, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE1-NEXT: retl
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;
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@ -660,17 +659,16 @@ define float @load_float_seq_cst(float* %fptr) {
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define double @load_double_seq_cst(double* %fptr) {
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; X86-SSE1-LABEL: load_double_seq_cst:
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; X86-SSE1: # %bb.0:
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; X86-SSE1-NEXT: subl $20, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 24
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; X86-SSE1-NEXT: subl $12, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 16
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: fildll (%eax)
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; X86-SSE1-NEXT: fistpll {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: movl %eax, (%esp)
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; X86-SSE1-NEXT: xorps %xmm0, %xmm0
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; X86-SSE1-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; X86-SSE1-NEXT: movss %xmm0, (%esp)
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; X86-SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
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; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
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; X86-SSE1-NEXT: fldl (%esp)
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; X86-SSE1-NEXT: addl $20, %esp
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; X86-SSE1-NEXT: addl $12, %esp
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; X86-SSE1-NEXT: .cfi_def_cfa_offset 4
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; X86-SSE1-NEXT: retl
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;
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