forked from OSchip/llvm-project
[AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.
For vectors that are exactly equal to getMaxSVEVectorSizeInBits, just use AArch64SVEPredPattern::all, which can enable the use of unpredicated ptrue when available. TestPlan: check-llvm Differential Revision: https://reviews.llvm.org/D108706
This commit is contained in:
Jun Ma
parent
8c47103491
commit
15b2a8e7fa
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@ -18026,9 +18026,16 @@ static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
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getSVEPredPatternFromNumElements(VT.getVectorNumElements());
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assert(PgPattern && "Unexpected element count for SVE predicate");
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// TODO: For vectors that are exactly getMaxSVEVectorSizeInBits big, we can
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// use AArch64SVEPredPattern::all, which can enable the use of unpredicated
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// For vectors that are exactly getMaxSVEVectorSizeInBits big, we can use
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// AArch64SVEPredPattern::all, which can enable the use of unpredicated
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// variants of instructions when available.
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const auto &Subtarget =
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static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
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unsigned MinSVESize = Subtarget.getMinSVEVectorSizeInBits();
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unsigned MaxSVESize = Subtarget.getMaxSVEVectorSizeInBits();
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if (MaxSVESize && MinSVESize == MaxSVESize &&
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MaxSVESize == VT.getSizeInBits())
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PgPattern = AArch64SVEPredPattern::all;
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MVT MaskVT;
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switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
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@ -226,18 +226,17 @@ define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(<vsca
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ptrue p1.s, vl8
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: ld1w { z1.s }, p1/z, [x1]
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; CHECK-NEXT: subs x8, x8, #8
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; CHECK-NEXT: csel x8, xzr, x8, lo
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; CHECK-NEXT: mov w9, #8
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; CHECK-NEXT: cmp x8, #8
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; CHECK-NEXT: ptrue p1.d, vl8
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: uunpklo z0.d, z1.s
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1d { z0.d }, p1, [x9, x8, lsl #3]
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; CHECK-NEXT: st1d { z0.d }, p0, [x9, x8, lsl #3]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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@ -186,12 +186,11 @@ define <4 x i64> @extract_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov w10, #4
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; CHECK-NEXT: cmp x9, #4
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; CHECK-NEXT: ptrue p1.d, vl4
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: csel x9, x9, x10, lo
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; CHECK-NEXT: mov x10, sp
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; CHECK-NEXT: ld1d { z0.d }, p1/z, [x10, x9, lsl #3]
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; CHECK-NEXT: st1d { z0.d }, p1, [x8]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x10, x9, lsl #3]
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; CHECK-NEXT: st1d { z0.d }, p0, [x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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@ -0,0 +1,117 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-max=512 < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
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; CHECK-LABEL: add_v64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z1.b }, p0/z, [x1]
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; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <64 x i8>, <64 x i8>* %a
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%op2 = load <64 x i8>, <64 x i8>* %b
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%res = add <64 x i8> %op1, %op2
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store <64 x i8> %res, <64 x i8>* %a
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ret void
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}
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define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b, <32 x i16>* %c) #0 {
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; CHECK-LABEL: add_v32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i16>, <32 x i16>* %a
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%op2 = load <32 x i16>, <32 x i16>* %b
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%res = add <32 x i16> %op1, %op2
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store <32 x i16> %res, <32 x i16>* %a
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ret void
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}
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define void @abs_v16i32(<16 x i32>* %a) #0 {
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; CHECK-LABEL: abs_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: abs z0.s, p0/m, z0.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, <16 x i32>* %a
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%res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false)
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store <16 x i32> %res, <16 x i32>* %a
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ret void
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}
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define void @abs_v8i64(<8 x i64>* %a) #0 {
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; CHECK-LABEL: abs_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: abs z0.d, p0/m, z0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i64>, <8 x i64>* %a
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%res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false)
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store <8 x i64> %res, <8 x i64>* %a
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ret void
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}
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define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
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; CHECK-LABEL: fadd_v32f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: fadd z0.h, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x half>, <32 x half>* %a
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%op2 = load <32 x half>, <32 x half>* %b
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%res = fadd <32 x half> %op1, %op2
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store <32 x half> %res, <32 x half>* %a
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ret void
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}
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define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
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; CHECK-LABEL: fadd_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fadd z0.s, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x float>, <16 x float>* %a
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%op2 = load <16 x float>, <16 x float>* %b
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%res = fadd <16 x float> %op1, %op2
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store <16 x float> %res, <16 x float>* %a
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ret void
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}
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define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
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; CHECK-LABEL: fadd_v8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
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; CHECK-NEXT: fadd z0.d, z0.d, z1.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x double>, <8 x double>* %a
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%op2 = load <8 x double>, <8 x double>* %b
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%res = fadd <8 x double> %op1, %op2
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store <8 x double> %res, <8 x double>* %a
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ret void
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}
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declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)
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declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)
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attributes #0 = { "target-features"="+sve" }
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@ -329,19 +329,18 @@ define <vscale x 2 x i64> @insert_fixed_v4i64_nxv2i64(<vscale x 2 x i64> %vec, <
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]
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; CHECK-NEXT: subs x8, x8, #4
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; CHECK-NEXT: csel x8, xzr, x8, lo
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; CHECK-NEXT: mov w9, #4
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; CHECK-NEXT: cmp x8, #4
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: st1d { z0.d }, p1, [sp]
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: st1d { z1.d }, p0, [x9, x8, lsl #3]
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; CHECK-NEXT: ld1d { z0.d }, p1/z, [sp]
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [sp]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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@ -63,7 +63,7 @@ define void @func_vscale2_2(<16 x i32>* %a, <16 x i32>* %b) #2 {
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; CHECK-LABEL: func_vscale2_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #8
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z2.s }, p0/z, [x1, x8, lsl #2]
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@ -108,7 +108,7 @@ attributes #3 = { "target-features"="+sve" vscale_range(2,4) }
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define void @func_vscale4_4(<16 x i32>* %a, <16 x i32>* %b) #4 {
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; CHECK-LABEL: func_vscale4_4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl16
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
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