forked from OSchip/llvm-project
[AArch64][SME] Add system registers and related instructions
This patch adds the new system registers introduced in SME:
- ID_AA64SMFR0_EL1 (ro) SME feature identifier.
- SMCR_ELx (r/w) streaming mode control register for configuring
effective SVE Streaming SVE Vector length when the PE is in
Streaming SVE mode.
- SVCR (r/w) streaming vector control register, visible at all
exception levels. Provides access to PSTATE.SM and PSTATE.ZA
using MSR and MRS instructions.
- SMPRI_EL1 (r/w) streaming mode execution priority register.
- SMPRIMAP_EL2 (r/w) streaming mode priority mapping register.
- SMIDR_EL1 (ro) streaming mode identification register.
- TPIDR2_EL0 (r/w) for use by SME software to manage per-thread
SME context.
- MPAMSM_EL1 (r/w) MPAM (v8.4) streaming mode register, for
labelling memory accesses performed in streaming mode.
Also added in this patch are the SME mode change instructions.
Three MSR immediate instructions are implemented to set or clear
PSTATE.SM, PSTATE.ZA, or both respectively:
- MSR SVCRSM, #<imm1>
- MSR SVCRZA, #<imm1>
- MSR SVCRSMZA, #<imm1>
The following smstart/smstop aliases are also implemented for
convenience:
smstart -> MSR SVCRSMZA, #1
smstart sm -> MSR SVCRSM, #1
smstart za -> MSR SVCRZA, #1
smstop -> MSR SVCRSMZA, #0
smstop sm -> MSR SVCRSM, #0
smstop za -> MSR SVCRZA, #0
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D105576
This commit is contained in:
Cullen Rhodes
parent
b4001ae885
commit
15af3aaa2e
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@ -1356,3 +1356,20 @@ def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u"
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def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
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let EncoderMethod = "encodeMatrixIndexGPR32";
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}
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def SVCROperand : AsmOperandClass {
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let Name = "SVCR";
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let ParserMethod = "tryParseSVCR";
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let DiagnosticType = "Invalid" # Name;
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}
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def svcr_op : Operand<i32> {
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let ParserMatchClass = SVCROperand;
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let PrintMethod = "printSVCROp";
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let DecoderMethod = "DecodeSVCROp";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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return AArch64SVCR::lookupSVCRByEncoding(MCOp.getImm()) != nullptr;
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}];
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}
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@ -74,6 +74,41 @@ let Predicates = [HasSME] in {
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defm LD1_MXIPXX : sme_mem_ld_ss<"ld1">;
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defm ST1_MXIPXX : sme_mem_st_ss<"st1">;
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//===----------------------------------------------------------------------===//
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// Mode selection and state access instructions
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//===----------------------------------------------------------------------===//
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// SME defines three pstate fields to set or clear PSTATE.SM, PSTATE.ZA, or
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// both fields:
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//
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// MSR SVCRSM, #<imm1>
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// MSR SVCRZA, #<imm1>
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// MSR SVCRSMZA, #<imm1>
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//
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// It's tricky to using the existing pstate operand defined in
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// AArch64SystemOperands.td since it only encodes 5 bits including op1;op2,
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// when these fields are also encoded in CRm[3:1].
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class MSRpstatesvcrImm0_1
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: PstateWriteSimple<(ins svcr_op:$pstatefield, imm0_1:$imm), "msr",
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"\t$pstatefield, $imm">,
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Sched<[WriteSys]> {
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bits<3> pstatefield;
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bit imm;
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let Inst{18-16} = 0b011; // op1
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let Inst{11-9} = pstatefield;
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let Inst{8} = imm;
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let Inst{7-5} = 0b011; // op2
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}
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def MSRpstatesvcrImm1 : MSRpstatesvcrImm0_1;
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def : InstAlias<"smstart", (MSRpstatesvcrImm1 0b011, 0b1)>;
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def : InstAlias<"smstart sm", (MSRpstatesvcrImm1 0b001, 0b1)>;
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def : InstAlias<"smstart za", (MSRpstatesvcrImm1 0b010, 0b1)>;
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def : InstAlias<"smstop", (MSRpstatesvcrImm1 0b011, 0b0)>;
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def : InstAlias<"smstop sm", (MSRpstatesvcrImm1 0b001, 0b0)>;
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def : InstAlias<"smstop za", (MSRpstatesvcrImm1 0b010, 0b0)>;
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//===----------------------------------------------------------------------===//
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// SVE2 instructions
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//===----------------------------------------------------------------------===//
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@ -368,6 +368,26 @@ def : PState<"SSBS", 0b11001>;
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let Requires = [{ {AArch64::FeatureMTE} }] in
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def : PState<"TCO", 0b11100>;
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//===----------------------------------------------------------------------===//
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// SVCR instruction options.
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//===----------------------------------------------------------------------===//
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class SVCR<string name, bits<3> encoding> : SearchableTable {
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let SearchableFields = ["Name", "Encoding"];
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let EnumValueField = "Encoding";
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string Name = name;
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bits<3> Encoding;
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let Encoding = encoding;
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code Requires = [{ {} }];
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}
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let Requires = [{ {AArch64::FeatureSME} }] in {
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def : SVCR<"SVCRSM", 0b001>;
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def : SVCR<"SVCRZA", 0b010>;
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def : SVCR<"SVCRSMZA", 0b011>;
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}
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//===----------------------------------------------------------------------===//
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// PSB instruction options.
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//===----------------------------------------------------------------------===//
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@ -758,6 +778,12 @@ def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
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def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
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}
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// v9-a Scalable Matrix Extension (SME) registers
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::FeatureSME} }] in {
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def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;
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}
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//===----------------------
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// Write-only regs
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//===----------------------
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@ -1616,3 +1642,23 @@ def : RWSysReg<"PMSNEVFR_EL1", 0b11, 0b000, 0b1001, 0b1001, 0b001>;
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::ProcAppleA7} }] in
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def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;
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// Scalable Matrix Extension (SME)
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::FeatureSME} }] in {
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def : RWSysReg<"SMCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b110>;
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def : RWSysReg<"SMCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b110>;
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def : RWSysReg<"SMCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b110>;
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def : RWSysReg<"SMCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b110>;
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def : RWSysReg<"SVCR", 0b11, 0b011, 0b0100, 0b0010, 0b010>;
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def : RWSysReg<"SMPRI_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b100>;
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def : RWSysReg<"SMPRIMAP_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b101>;
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def : ROSysReg<"SMIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b110>;
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def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>;
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} // HasSME
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// v8.4a MPAM and SME registers
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
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def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>;
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} // HasMPAM, HasSME
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@ -233,6 +233,7 @@ private:
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OperandMatchResultTy tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
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RegKind MatchKind);
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OperandMatchResultTy tryParseMatrixRegister(OperandVector &Operands);
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OperandMatchResultTy tryParseSVCR(OperandVector &Operands);
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OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
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OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
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OperandMatchResultTy tryParseBarriernXSOperand(OperandVector &Operands);
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@ -321,6 +322,7 @@ private:
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k_CondCode,
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k_Register,
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k_MatrixRegister,
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k_SVCR,
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k_VectorList,
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k_VectorIndex,
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k_Token,
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@ -448,6 +450,12 @@ private:
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unsigned Val;
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};
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struct SVCROp {
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const char *Data;
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unsigned Length;
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unsigned PStateField;
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};
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union {
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struct TokOp Tok;
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struct RegOp Reg;
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@ -465,6 +473,7 @@ private:
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struct PSBHintOp PSBHint;
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struct BTIHintOp BTIHint;
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struct ShiftExtendOp ShiftExtend;
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struct SVCROp SVCR;
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};
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// Keep the MCContext around as the MCExprs may need manipulated during
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@ -527,6 +536,9 @@ public:
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case k_ShiftExtend:
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ShiftExtend = o.ShiftExtend;
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break;
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case k_SVCR:
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SVCR = o.SVCR;
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break;
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}
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}
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@ -665,6 +677,11 @@ public:
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return StringRef(BTIHint.Data, BTIHint.Length);
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}
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StringRef getSVCR() const {
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assert(Kind == k_SVCR && "Invalid access!");
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return StringRef(SVCR.Data, SVCR.Length);
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}
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StringRef getPrefetchName() const {
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assert(Kind == k_Prefetch && "Invalid access!");
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return StringRef(Prefetch.Data, Prefetch.Length);
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@ -1099,6 +1116,12 @@ public:
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return SysReg.PStateField != -1U;
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}
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bool isSVCR() const {
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if (Kind != k_SVCR)
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return false;
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return SVCR.PStateField != -1U;
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}
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bool isReg() const override {
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return Kind == k_Register;
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}
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@ -1809,6 +1832,12 @@ public:
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Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
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}
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void addSVCROperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createImm(SVCR.PStateField));
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}
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void addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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@ -2114,6 +2143,17 @@ public:
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return Op;
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}
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static std::unique_ptr<AArch64Operand>
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CreateSVCR(uint32_t PStateField, StringRef Str, SMLoc S, MCContext &Ctx) {
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auto Op = std::make_unique<AArch64Operand>(k_SVCR, Ctx);
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Op->SVCR.PStateField = PStateField;
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Op->SVCR.Data = Str.data();
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Op->SVCR.Length = Str.size();
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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static std::unique_ptr<AArch64Operand>
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CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,
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bool HasExplicitAmount, SMLoc S, SMLoc E, MCContext &Ctx) {
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@ -2195,6 +2235,10 @@ void AArch64Operand::print(raw_ostream &OS) const {
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case k_MatrixRegister:
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OS << "<matrix " << getMatrixReg() << ">";
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break;
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case k_SVCR: {
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OS << getSVCR();
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break;
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}
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case k_Register:
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OS << "<register " << getReg() << ">";
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if (!getShiftExtendAmount() && !hasShiftExtendAmount())
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@ -2975,6 +3019,28 @@ bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
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return false;
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}
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OperandMatchResultTy
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AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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const AsmToken &Tok = Parser.getTok();
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SMLoc S = getLoc();
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if (Tok.isNot(AsmToken::Identifier)) {
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TokError("invalid operand for instruction");
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return MatchOperand_ParseFail;
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}
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unsigned PStateImm = -1;
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const auto *SVCR = AArch64SVCR::lookupSVCRByName(Tok.getString());
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if (SVCR && SVCR->haveFeatures(getSTI().getFeatureBits()))
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PStateImm = SVCR->Encoding;
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Operands.push_back(
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AArch64Operand::CreateSVCR(PStateImm, Tok.getString(), S, getContext()));
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Parser.Lex(); // Eat identifier token.
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return MatchOperand_Success;
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}
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OperandMatchResultTy
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AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
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MCAsmParser &Parser = getParser();
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@ -3431,6 +3497,9 @@ AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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if (AArch64SVCR::lookupSVCRByName(Tok.getString()))
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return MatchOperand_NoMatch;
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int MRSReg, MSRReg;
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auto SysReg = AArch64SysReg::lookupSysRegByName(Tok.getString());
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if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
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@ -3946,8 +4015,15 @@ bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
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auto Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return true;
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Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
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Tok.getLoc(), getContext()));
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auto Keyword = Tok.getString();
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Keyword = StringSwitch<StringRef>(Keyword.lower())
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.Case("sm", "sm")
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.Case("za", "za")
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.Default(Keyword);
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Operands.push_back(
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AArch64Operand::CreateToken(Keyword, false, Tok.getLoc(), getContext()));
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Parser.Lex();
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return false;
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}
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@ -4021,6 +4097,11 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
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if (!parseOptionalMulOperand(Operands))
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return false;
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// If this is an "smstart" or "smstop" instruction, parse its special
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// keyword operand as an identifier.
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if (Mnemonic == "smstart" || Mnemonic == "smstop")
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return parseKeywordOperand(Operands);
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// This could be an optional "shift" or "extend" operand.
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OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
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// We can only continue if no tokens were eaten.
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@ -4876,6 +4957,7 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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case Match_MRS:
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return Error(Loc, "expected readable system register");
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case Match_MSR:
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case Match_InvalidSVCR:
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return Error(Loc, "expected writable system register or pstate");
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case Match_InvalidComplexRotationEven:
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return Error(Loc, "complex rotation must be 0, 90, 180 or 270.");
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@ -5551,6 +5633,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidMatrixTileVectorV32:
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case Match_InvalidMatrixTileVectorV64:
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case Match_InvalidMatrixTileVectorV128:
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case Match_InvalidSVCR:
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case Match_MSR:
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case Match_MRS: {
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if (ErrorInfo >= Operands.size())
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@ -6435,6 +6518,14 @@ unsigned AArch64AsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
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case MCK__HASH_8:
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ExpectedVal = 8;
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break;
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case MCK_MPR:
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// If the Kind is a token for the MPR register class which has the "za"
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// register (SME accumulator array), check if the asm is a literal "za"
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// token. This is for the "smstart za" alias that defines the register
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// as a literal token.
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if (Op.isTokenEqual("za"))
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return Match_Success;
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break;
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}
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if (!Op.isImm())
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return Match_InvalidOperand;
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@ -233,6 +233,8 @@ static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder);
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static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
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uint64_t Addr, const void *Decoder);
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static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
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const void *Decoder);
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static bool Check(DecodeStatus &Out, DecodeStatus In) {
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switch (In) {
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@ -1992,3 +1994,12 @@ static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
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Inst.addOperand(MCOperand::createImm(Imm + 1));
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return Success;
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}
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static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
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const void *Decoder) {
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if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
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Inst.addOperand(MCOperand::createImm(Imm));
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return Success;
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}
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return Fail;
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}
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@ -933,6 +933,17 @@ void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
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O << getRegisterName(RegOp.getReg());
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}
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void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNum);
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assert(MO.isImm() && "Unexpected operand type!");
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unsigned svcrop = MO.getImm();
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const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
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assert(SVCR && "Unexpected SVCR operand!");
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||||
O << SVCR->Name;
|
||||
}
|
||||
|
||||
void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
|
|
|
|||
|
|
@ -196,6 +196,8 @@ protected:
|
|||
template <int EltSize>
|
||||
void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
template <char = 0>
|
||||
void printSVERegOp(const MCInst *MI, unsigned OpNum,
|
||||
const MCSubtargetInfo &STI, raw_ostream &O);
|
||||
|
|
|
|||
|
|
@ -169,3 +169,10 @@ namespace llvm {
|
|||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
namespace AArch64SVCR {
|
||||
#define GET_SVCR_IMPL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -346,6 +346,14 @@ struct SysAliasImm : SysAlias {
|
|||
: SysAlias(N, E, F), ImmValue(I) {}
|
||||
};
|
||||
|
||||
namespace AArch64SVCR {
|
||||
struct SVCR : SysAlias{
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_SVCR_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64AT{
|
||||
struct AT : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid keyword
|
||||
|
||||
smstart foo
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: smstart foo
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
smstart
|
||||
// CHECK-INST: smstart
|
||||
// CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 47 03 d5 msr S0_3_C4_C7_3, xzr
|
||||
|
||||
smstart sm
|
||||
// CHECK-INST: smstart sm
|
||||
// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 43 03 d5 msr S0_3_C4_C3_3, xzr
|
||||
|
||||
smstart za
|
||||
// CHECK-INST: smstart za
|
||||
// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 45 03 d5 msr S0_3_C4_C5_3, xzr
|
||||
|
||||
smstart SM
|
||||
// CHECK-INST: smstart sm
|
||||
// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 43 03 d5 msr S0_3_C4_C3_3, xzr
|
||||
|
||||
smstart ZA
|
||||
// CHECK-INST: smstart za
|
||||
// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 45 03 d5 msr S0_3_C4_C5_3, xzr
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid keyword
|
||||
|
||||
smstop foo
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: smstop foo
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
smstop
|
||||
// CHECK-INST: smstop
|
||||
// CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 46 03 d5 msr S0_3_C4_C6_3, xzr
|
||||
|
||||
smstop sm
|
||||
// CHECK-INST: smstop sm
|
||||
// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 42 03 d5 msr S0_3_C4_C2_3, xzr
|
||||
|
||||
smstop za
|
||||
// CHECK-INST: smstop za
|
||||
// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 44 03 d5 msr S0_3_C4_C4_3, xzr
|
||||
|
||||
smstop SM
|
||||
// CHECK-INST: smstop sm
|
||||
// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 42 03 d5 msr S0_3_C4_C2_3, xzr
|
||||
|
||||
smstop ZA
|
||||
// CHECK-INST: smstop za
|
||||
// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
|
||||
// CHECK-ERROR: instruction requires: sme
|
||||
// CHECK-UNKNOWN: 7f 44 03 d5 msr S0_3_C4_C4_3, xzr
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
// RUN: not llvm-mc -triple aarch64 -mattr=+sme -show-encoding < %s 2>&1 | FileCheck %s
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Check read-only
|
||||
|
||||
msr ID_AA64SMFR0_EL1, x3
|
||||
// CHECK: error: expected writable system register or pstate
|
||||
// CHECK-NEXT: msr ID_AA64SMFR0_EL1, x3
|
||||
|
||||
msr SMIDR_EL1, x3
|
||||
// CHECK: error: expected writable system register or pstate
|
||||
// CHECK-NEXT: msr SMIDR_EL1, x3
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Check MSR SVCR immediate is in range [0, 1]
|
||||
|
||||
msr SVCRSM, #-1
|
||||
// CHECK: error: immediate must be an integer in range [0, 1].
|
||||
// CHECK-NEXT: msr SVCRSM, #-1
|
||||
|
||||
msr SVCRZA, #2
|
||||
// CHECK: error: immediate must be an integer in range [0, 1].
|
||||
// CHECK-NEXT: msr SVCRZA, #2
|
||||
|
||||
msr SVCRSMZA, #4
|
||||
// CHECK: error: immediate must be an integer in range [0, 1].
|
||||
// CHECK-NEXT: msr SVCRSMZA, #4
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+mpam < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+mpam < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+sme,+mpam - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+mpam - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// read
|
||||
|
||||
mrs x3, MPAMSM_EL1
|
||||
// CHECK-INST: mrs x3, MPAMSM_EL1
|
||||
// CHECK-ENCODING: [0x63,0xa5,0x38,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: 63 a5 38 d5 mrs x3, S3_0_C10_C5_3
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// write
|
||||
|
||||
msr MPAMSM_EL1, x3
|
||||
// CHECK-INST: msr MPAMSM_EL1, x3
|
||||
// CHECK-ENCODING: [0x63,0xa5,0x18,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 63 a5 18 d5 msr S3_0_C10_C5_3, x3
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// read
|
||||
|
||||
mrs x3, ID_AA64SMFR0_EL1
|
||||
// CHECK-INST: mrs x3, ID_AA64SMFR0_EL1
|
||||
// CHECK-ENCODING: [0xa3,0x04,0x38,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: a3 04 38 d5 mrs x3, S3_0_C0_C4_5
|
||||
|
||||
mrs x3, SMCR_EL1
|
||||
// CHECK-INST: mrs x3, SMCR_EL1
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x38,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: c3 12 38 d5 mrs x3, S3_0_C1_C2_6
|
||||
|
||||
mrs x3, SMCR_EL2
|
||||
// CHECK-INST: mrs x3, SMCR_EL2
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x3c,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: c3 12 3c d5 mrs x3, S3_4_C1_C2_6
|
||||
|
||||
mrs x3, SMCR_EL3
|
||||
// CHECK-INST: mrs x3, SMCR_EL3
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x3e,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: c3 12 3e d5 mrs x3, S3_6_C1_C2_6
|
||||
|
||||
mrs x3, SMCR_EL12
|
||||
// CHECK-INST: mrs x3, SMCR_EL12
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x3d,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: c3 12 3d d5 mrs x3, S3_5_C1_C2_6
|
||||
|
||||
mrs x3, SVCR
|
||||
// CHECK-INST: mrs x3, SVCR
|
||||
// CHECK-ENCODING: [0x43,0x42,0x3b,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: 43 42 3b d5 mrs x3, S3_3_C4_C2_2
|
||||
|
||||
mrs x3, SMPRI_EL1
|
||||
// CHECK-INST: mrs x3, SMPRI_EL1
|
||||
// CHECK-ENCODING: [0x83,0x12,0x38,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: 83 12 38 d5 mrs x3, S3_0_C1_C2_4
|
||||
|
||||
mrs x3, SMPRIMAP_EL2
|
||||
// CHECK-INST: mrs x3, SMPRIMAP_EL2
|
||||
// CHECK-ENCODING: [0xa3,0x12,0x3c,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: a3 12 3c d5 mrs x3, S3_4_C1_C2_5
|
||||
|
||||
mrs x3, SMIDR_EL1
|
||||
// CHECK-INST: mrs x3, SMIDR_EL1
|
||||
// CHECK-ENCODING: [0xc3,0x00,0x39,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: c3 00 39 d5 mrs x3, S3_1_C0_C0_6
|
||||
|
||||
mrs x3, TPIDR2_EL0
|
||||
// CHECK-INST: mrs x3, TPIDR2_EL0
|
||||
// CHECK-ENCODING: [0xa3,0xd0,0x3b,0xd5]
|
||||
// CHECK-ERROR: expected readable system register
|
||||
// CHECK-UNKNOWN: a3 d0 3b d5 mrs x3, S3_3_C13_C0_5
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// write
|
||||
|
||||
msr SMCR_EL1, x3
|
||||
// CHECK-INST: msr SMCR_EL1, x3
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x18,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: c3 12 18 d5 msr S3_0_C1_C2_6, x3
|
||||
|
||||
msr SMCR_EL2, x3
|
||||
// CHECK-INST: msr SMCR_EL2, x3
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x1c,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: c3 12 1c d5 msr S3_4_C1_C2_6, x3
|
||||
|
||||
msr SMCR_EL3, x3
|
||||
// CHECK-INST: msr SMCR_EL3, x3
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x1e,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: c3 12 1e d5 msr S3_6_C1_C2_6, x3
|
||||
|
||||
msr SMCR_EL12, x3
|
||||
// CHECK-INST: msr SMCR_EL12, x3
|
||||
// CHECK-ENCODING: [0xc3,0x12,0x1d,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: c3 12 1d d5 msr S3_5_C1_C2_6, x3
|
||||
|
||||
msr SVCR, x3
|
||||
// CHECK-INST: msr SVCR, x3
|
||||
// CHECK-ENCODING: [0x43,0x42,0x1b,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 43 42 1b d5 msr S3_3_C4_C2_2, x3
|
||||
|
||||
msr SMPRI_EL1, x3
|
||||
// CHECK-INST: msr SMPRI_EL1, x3
|
||||
// CHECK-ENCODING: [0x83,0x12,0x18,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 83 12 18 d5 msr S3_0_C1_C2_4, x3
|
||||
|
||||
msr SMPRIMAP_EL2, x3
|
||||
// CHECK-INST: msr SMPRIMAP_EL2, x3
|
||||
// CHECK-ENCODING: [0xa3,0x12,0x1c,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: a3 12 1c d5 msr S3_4_C1_C2_5, x3
|
||||
|
||||
msr SVCRSM, #0
|
||||
// CHECK-INST: smstop sm
|
||||
// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 42 03 d5 msr S0_3_C4_C2_3, xzr
|
||||
|
||||
msr SVCRSM, #1
|
||||
// CHECK-INST: smstart
|
||||
// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 43 03 d5 msr S0_3_C4_C3_3, xzr
|
||||
|
||||
msr SVCRZA, #0
|
||||
// CHECK-INST: smstop za
|
||||
// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 44 03 d5 msr S0_3_C4_C4_3, xzr
|
||||
|
||||
msr SVCRZA, #1
|
||||
// CHECK-INST: smstart za
|
||||
// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 45 03 d5 msr S0_3_C4_C5_3, xzr
|
||||
|
||||
msr SVCRSMZA, #0
|
||||
// CHECK-INST: smstop
|
||||
// CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 46 03 d5 msr S0_3_C4_C6_3, xzr
|
||||
|
||||
msr SVCRSMZA, #1
|
||||
// CHECK-INST: smstart
|
||||
// CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: 7f 47 03 d5 msr S0_3_C4_C7_3, xzr
|
||||
|
||||
msr TPIDR2_EL0, x3
|
||||
// CHECK-INST: msr TPIDR2_EL0, x3
|
||||
// CHECK-ENCODING: [0xa3,0xd0,0x1b,0xd5]
|
||||
// CHECK-ERROR: expected writable system register or pstate
|
||||
// CHECK-UNKNOWN: a3 d0 1b d5 msr S3_3_C13_C0_5, x3
|
||||
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Reference in New Issue