forked from OSchip/llvm-project
[InstCombine] Add more tests for signed saturing math overflow; NFC
Overflow conditions for sadd.sat and ssub.sat which can be determined based on constant ranges, but not necessarily known bits. llvm-svn: 357938
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Nikita Popov
parent
fa8185c504
commit
15abd74de7
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@ -375,8 +375,8 @@ define i8 @test_scalar_uadd_urem_may_ov(i8 %a) {
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}
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; We have a constant range for the LHS, but only known bits for the RHS
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define i8 @test_scalar_uadd_urem_known_bits(i8 %a, i8 %b) {
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; CHECK-LABEL: @test_scalar_uadd_urem_known_bits(
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define i8 @test_scalar_uadd_udiv_known_bits(i8 %a, i8 %b) {
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; CHECK-LABEL: @test_scalar_uadd_udiv_known_bits(
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; CHECK-NEXT: [[AA:%.*]] = udiv i8 -66, [[A:%.*]]
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; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 63
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; CHECK-NEXT: [[R:%.*]] = add nuw i8 [[AA]], [[BB]]
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@ -388,6 +388,41 @@ define i8 @test_scalar_uadd_urem_known_bits(i8 %a, i8 %b) {
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ret i8 %r
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}
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define i8 @test_scalar_sadd_srem_no_ov(i8 %a) {
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; CHECK-LABEL: @test_scalar_sadd_srem_no_ov(
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; CHECK-NEXT: [[B:%.*]] = srem i8 [[A:%.*]], 100
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[B]], i8 28)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%b = srem i8 %a, 100
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%r = call i8 @llvm.sadd.sat.i8(i8 %b, i8 28)
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ret i8 %r
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}
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define i8 @test_scalar_sadd_srem_may_ov(i8 %a) {
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; CHECK-LABEL: @test_scalar_sadd_srem_may_ov(
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; CHECK-NEXT: [[B:%.*]] = srem i8 [[A:%.*]], 100
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[B]], i8 29)
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; CHECK-NEXT: ret i8 [[R]]
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;
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%b = srem i8 %a, 100
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%r = call i8 @llvm.sadd.sat.i8(i8 %b, i8 29)
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ret i8 %r
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}
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define i8 @test_scalar_sadd_srem_and_no_ov(i8 %a, i8 %b) {
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; CHECK-LABEL: @test_scalar_sadd_srem_and_no_ov(
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; CHECK-NEXT: [[AA:%.*]] = srem i8 [[A:%.*]], 100
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; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 15
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[AA]], i8 [[BB]])
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; CHECK-NEXT: ret i8 [[R]]
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;
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%aa = srem i8 %a, 100
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%bb = and i8 %b, 15
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%r = call i8 @llvm.sadd.sat.i8(i8 %aa, i8 %bb)
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ret i8 %r
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}
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;
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; Saturating subtraction.
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;
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@ -889,6 +924,84 @@ define <2 x i8> @test_vector_usub_add_nuw_no_ov_nonsplat3(<2 x i8> %a) {
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ret <2 x i8> %r
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}
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define i8 @test_scalar_ssub_add_nsw_no_ov(i8 %a, i8 %b) {
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; CHECK-LABEL: @test_scalar_ssub_add_nsw_no_ov(
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; CHECK-NEXT: [[AA:%.*]] = add nsw i8 [[A:%.*]], 7
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; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 7
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[AA]], i8 [[BB]])
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; CHECK-NEXT: ret i8 [[R]]
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;
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%aa = add nsw i8 %a, 7
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%bb = and i8 %b, 7
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%r = call i8 @llvm.ssub.sat.i8(i8 %aa, i8 %bb)
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ret i8 %r
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}
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define i8 @test_scalar_ssub_add_nsw_may_ov(i8 %a, i8 %b) {
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; CHECK-LABEL: @test_scalar_ssub_add_nsw_may_ov(
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; CHECK-NEXT: [[AA:%.*]] = add nsw i8 [[A:%.*]], 6
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; CHECK-NEXT: [[BB:%.*]] = and i8 [[B:%.*]], 7
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[AA]], i8 [[BB]])
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; CHECK-NEXT: ret i8 [[R]]
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;
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%aa = add nsw i8 %a, 6
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%bb = and i8 %b, 7
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%r = call i8 @llvm.ssub.sat.i8(i8 %aa, i8 %bb)
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ret i8 %r
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}
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define <2 x i8> @test_vector_ssub_add_nsw_no_ov_splat(<2 x i8> %a, <2 x i8> %b) {
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; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_splat(
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; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 7>
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; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 7>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%aa = add nsw <2 x i8> %a, <i8 7, i8 7>
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%bb = and <2 x i8> %b, <i8 7, i8 7>
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%r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
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ret <2 x i8> %r
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}
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define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat1(<2 x i8> %a, <2 x i8> %b) {
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; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat1(
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; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 7>
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; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 6>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%aa = add nsw <2 x i8> %a, <i8 7, i8 7>
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%bb = and <2 x i8> %b, <i8 7, i8 6>
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%r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
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ret <2 x i8> %r
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}
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define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat2(<2 x i8> %a, <2 x i8> %b) {
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; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat2(
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; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 8>
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; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 7>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%aa = add nsw <2 x i8> %a, <i8 7, i8 8>
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%bb = and <2 x i8> %b, <i8 7, i8 7>
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%r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
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ret <2 x i8> %r
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}
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define <2 x i8> @test_vector_ssub_add_nsw_no_ov_nonsplat3(<2 x i8> %a, <2 x i8> %b) {
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; CHECK-LABEL: @test_vector_ssub_add_nsw_no_ov_nonsplat3(
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; CHECK-NEXT: [[AA:%.*]] = add nsw <2 x i8> [[A:%.*]], <i8 7, i8 6>
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; CHECK-NEXT: [[BB:%.*]] = and <2 x i8> [[B:%.*]], <i8 7, i8 6>
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; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> [[AA]], <2 x i8> [[BB]])
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%aa = add nsw <2 x i8> %a, <i8 7, i8 6>
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%bb = and <2 x i8> %b, <i8 7, i8 6>
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%r = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %aa, <2 x i8> %bb)
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ret <2 x i8> %r
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}
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; Raw IR tests
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define i32 @uadd_sat(i32 %x, i32 %y) {
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