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[RISCV] Remove stale references to experimental-b. NFC 

Differential Revision: https://reviews.llvm.org/D117136
This commit is contained in:
Craig Topper 2022-01-12 12:13:03 -08:00
parent 6bd127b079
commit 15a78f9d09
24 changed files with 45 additions and 45 deletions
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8
llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
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@ -168,8 +168,8 @@ define i32 @rol_i32(i32 %a, i32 %b) nounwind {
ret i32 %or ret i32 %or
} }
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
@ -276,8 +276,8 @@ define i32 @ror_i32(i32 %a, i32 %b) nounwind {
ret i32 %or ret i32 %or
} }
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)

16
llvm/test/CodeGen/RISCV/rv32zbb.ll
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@ -502,8 +502,8 @@ define i32 @min_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @min_i64(i64 %a, i64 %b) nounwind { define i64 @min_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: min_i64: ; RV32I-LABEL: min_i64:
@ -563,8 +563,8 @@ define i32 @max_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @max_i64(i64 %a, i64 %b) nounwind { define i64 @max_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: max_i64: ; RV32I-LABEL: max_i64:
@ -624,8 +624,8 @@ define i32 @minu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @minu_i64(i64 %a, i64 %b) nounwind { define i64 @minu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: minu_i64: ; RV32I-LABEL: minu_i64:
@ -685,8 +685,8 @@ define i32 @maxu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @maxu_i64(i64 %a, i64 %b) nounwind { define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: maxu_i64: ; RV32I-LABEL: maxu_i64:

8
llvm/test/CodeGen/RISCV/rv32zbp.ll
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@ -2854,8 +2854,8 @@ define i32 @pack_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @pack_i64(i64 %a, i64 %b) nounwind { define i64 @pack_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: pack_i64: ; RV32I-LABEL: pack_i64:
@ -2894,8 +2894,8 @@ define i32 @packu_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @packu_i64(i64 %a, i64 %b) nounwind { define i64 @packu_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: packu_i64: ; RV32I-LABEL: packu_i64:

12
llvm/test/CodeGen/RISCV/rv32zbs.ll
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@ -132,8 +132,8 @@ define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @bset_i64(i64 %a, i64 %b) nounwind { define i64 @bset_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: bset_i64: ; RV32I-LABEL: bset_i64:
@ -211,8 +211,8 @@ define i32 @binv_i32(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @binv_i64(i64 %a, i64 %b) nounwind { define i64 @binv_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: binv_i64: ; RV32I-LABEL: binv_i64:
@ -274,8 +274,8 @@ define i32 @bext_i32_no_mask(i32 %a, i32 %b) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet any matching bit manipulation instructions on RV32. ; don't have yet any matching bit manipulation instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions suitable for this pattern. ; extensions introduce instructions suitable for this pattern.
define i64 @bext_i64(i64 %a, i64 %b) nounwind { define i64 @bext_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: bext_i64: ; RV32I-LABEL: bext_i64:

8
llvm/test/CodeGen/RISCV/rv32zbt.ll
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@ -332,8 +332,8 @@ define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet an efficient pattern-matching with bit manipulation ; don't have yet an efficient pattern-matching with bit manipulation
; instructions on RV32. ; instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions that can match more efficiently this pattern. ; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
@ -407,8 +407,8 @@ define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) nounwind {
; As we are not matching directly i64 code patterns on RV32 some i64 patterns ; As we are not matching directly i64 code patterns on RV32 some i64 patterns
; don't have yet an efficient pattern-matching with bit manipulation ; don't have yet an efficient pattern-matching with bit manipulation
; instructions on RV32. ; instructions on RV32.
; This test is presented here in case future expansions of the experimental-b ; This test is presented here in case future expansions of the Bitmanip
; extension introduce instructions that can match more efficiently this pattern. ; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)

2
llvm/test/MC/RISCV/rv32zba-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+zba < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbb-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+zbb < %s 2>&1 | FileCheck %s
# Too many operands # Too many operands
clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction

2
llvm/test/MC/RISCV/rv32zbbp-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
andn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction andn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbc-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbc < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+zbc < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbe-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbf-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbp-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
gorc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction gorc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbr-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
# Too many operands # Too many operands
crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction

2
llvm/test/MC/RISCV/rv32zbs-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbs < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+zbs < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv32zbt-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zba-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zba < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zbb-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zbb < %s 2>&1 | FileCheck %s
# Too many operands # Too many operands
clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction

2
llvm/test/MC/RISCV/rv64zbbp-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zbe-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zbf-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zbm-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbm < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbm < %s 2>&1 | FileCheck %s
# Too many operands # Too many operands
bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction

2
llvm/test/MC/RISCV/rv64zbp-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

2
llvm/test/MC/RISCV/rv64zbr-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
# Too many operands # Too many operands
crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction

2
llvm/test/MC/RISCV/rv64zbt-invalid.s
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@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
# Too few operands # Too few operands
fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction