forked from OSchip/llvm-project
[RISCV] Remove stale references to experimental-b. NFC
Differential Revision: https://reviews.llvm.org/D117136
This commit is contained in:
Craig Topper
parent
6bd127b079
commit
15a78f9d09
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@ -168,8 +168,8 @@ define i32 @rol_i32(i32 %a, i32 %b) nounwind {
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ret i32 %or
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}
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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@ -276,8 +276,8 @@ define i32 @ror_i32(i32 %a, i32 %b) nounwind {
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ret i32 %or
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}
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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@ -502,8 +502,8 @@ define i32 @min_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @min_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: min_i64:
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@ -563,8 +563,8 @@ define i32 @max_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @max_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: max_i64:
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@ -624,8 +624,8 @@ define i32 @minu_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @minu_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: minu_i64:
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@ -685,8 +685,8 @@ define i32 @maxu_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @maxu_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: maxu_i64:
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@ -2854,8 +2854,8 @@ define i32 @pack_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @pack_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: pack_i64:
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@ -2894,8 +2894,8 @@ define i32 @packu_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @packu_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: packu_i64:
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@ -132,8 +132,8 @@ define signext i32 @bset_i32_zero(i32 signext %a) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @bset_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: bset_i64:
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@ -211,8 +211,8 @@ define i32 @binv_i32(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @binv_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: binv_i64:
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@ -274,8 +274,8 @@ define i32 @bext_i32_no_mask(i32 %a, i32 %b) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions suitable for this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @bext_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: bext_i64:
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@ -332,8 +332,8 @@ define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet an efficient pattern-matching with bit manipulation
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; instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions that can match more efficiently this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions that can match more efficiently this pattern.
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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@ -407,8 +407,8 @@ define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) nounwind {
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet an efficient pattern-matching with bit manipulation
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; instructions on RV32.
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; This test is presented here in case future expansions of the experimental-b
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; extension introduce instructions that can match more efficiently this pattern.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions that can match more efficiently this pattern.
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+zba < %s 2>&1 | FileCheck %s
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# Too few operands
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sh1add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+zbb < %s 2>&1 | FileCheck %s
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# Too many operands
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clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
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# Too few operands
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andn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbc < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+zbc < %s 2>&1 | FileCheck %s
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# Too few operands
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clmul t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
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# Too few operands
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bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
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# Too few operands
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bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
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# Too few operands
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gorc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
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# Too many operands
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crc32.b t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,zbs < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+zbs < %s 2>&1 | FileCheck %s
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# Too few operands
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bclr t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
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# Too few operands
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cmix t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zba < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+zba < %s 2>&1 | FileCheck %s
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# Too few operands
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slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+zbb < %s 2>&1 | FileCheck %s
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# Too many operands
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clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,zbb,experimental-zbp < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+zbb,+experimental-zbp < %s 2>&1 | FileCheck %s
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# Too few operands
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rolw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbe < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbe < %s 2>&1 | FileCheck %s
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# Too few operands
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bdecompressw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbf < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbf < %s 2>&1 | FileCheck %s
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# Too few operands
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bfpw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbm < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbm < %s 2>&1 | FileCheck %s
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# Too many operands
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bmatflip t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbp < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbp < %s 2>&1 | FileCheck %s
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# Too few operands
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gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbr < %s 2>&1 | FileCheck %s
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# Too many operands
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crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
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@ -1,4 +1,4 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbt < %s 2>&1 | FileCheck %s
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zbt < %s 2>&1 | FileCheck %s
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# Too few operands
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fslw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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