forked from OSchip/llvm-project
[PowerPC] Replace subtract-from-zero float in version with fneg in PowerPC special fma compiler builtins
This is a re-revert with a corrected test. This patch adds a test for the PowerPC fma compiler builtins, some variations of which negate inputs and outputs. The code to generate IR for these builtins was untested before this patch. Originally, the code used the outdated method of subtracting floating point values from -0.0 as floating point negation. This patch remedies that. Patch by: Drew Wock <drew.wock@sas.com> Differential Revision: https://reviews.llvm.org/D76949
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@ -14056,7 +14056,6 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
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Value *X = EmitScalarExpr(E->getArg(0));
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Value *Y = EmitScalarExpr(E->getArg(1));
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Value *Z = EmitScalarExpr(E->getArg(2));
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Value *Zero = llvm::ConstantFP::getZeroValueForNegation(ResultType);
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llvm::Function *F = CGM.getIntrinsic(Intrinsic::fma, ResultType);
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switch (BuiltinID) {
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case PPC::BI__builtin_vsx_xvmaddadp:
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@ -14064,17 +14063,14 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
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return Builder.CreateCall(F, {X, Y, Z});
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case PPC::BI__builtin_vsx_xvnmaddadp:
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case PPC::BI__builtin_vsx_xvnmaddasp:
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return Builder.CreateFSub(Zero,
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Builder.CreateCall(F, {X, Y, Z}), "sub");
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return Builder.CreateFNeg(Builder.CreateCall(F, {X, Y, Z}), "neg");
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case PPC::BI__builtin_vsx_xvmsubadp:
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case PPC::BI__builtin_vsx_xvmsubasp:
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return Builder.CreateCall(F,
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{X, Y, Builder.CreateFSub(Zero, Z, "sub")});
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return Builder.CreateCall(F, {X, Y, Builder.CreateFNeg(Z, "neg")});
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case PPC::BI__builtin_vsx_xvnmsubadp:
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case PPC::BI__builtin_vsx_xvnmsubasp:
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Value *FsubRes =
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Builder.CreateCall(F, {X, Y, Builder.CreateFSub(Zero, Z, "sub")});
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return Builder.CreateFSub(Zero, FsubRes, "sub");
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return Builder.CreateFNeg(
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Builder.CreateCall(F, {X, Y, Builder.CreateFNeg(Z, "neg")}), "neg");
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}
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llvm_unreachable("Unknown FMA operation");
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return nullptr; // Suppress no-return warning
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@ -0,0 +1,43 @@
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// RUN: %clang_cc1 -triple powerpc64le-gnu-linux \
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// RUN: -target-feature +altivec -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck \
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// RUN: %s
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typedef __attribute__((vector_size(4 * sizeof(float)))) float vec_float;
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typedef __attribute__((vector_size(2 * sizeof(double)))) double vec_double;
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volatile vec_double vd;
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volatile vec_float vf;
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void test_fma(void) {
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vf = __builtin_vsx_xvmaddasp(vf, vf, vf);
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// CHECK: @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
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vd = __builtin_vsx_xvmaddadp(vd, vd, vd);
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// CHECK: @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
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vf = __builtin_vsx_xvnmaddasp(vf, vf, vf);
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// CHECK: [[RESULT:%[^ ]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}})
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// CHECK: fneg <4 x float> [[RESULT]]
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vd = __builtin_vsx_xvnmaddadp(vd, vd, vd);
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// CHECK: [[RESULT:%[^ ]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> %{{.*}})
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// CHECK: fneg <2 x double> [[RESULT]]
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vf = __builtin_vsx_xvmsubasp(vf, vf, vf);
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// CHECK: [[RESULT:%[^ ]+]] = fneg <4 x float> %{{.*}}
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// CHECK: @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[RESULT]])
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vd = __builtin_vsx_xvmsubadp(vd, vd, vd);
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// CHECK: [[RESULT:%[^ ]+]] = fneg <2 x double> %{{.*}}
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// CHECK: <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[RESULT]])
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vf = __builtin_vsx_xvnmsubasp(vf, vf, vf);
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// CHECK: [[RESULT:%[^ ]+]] = fneg <4 x float> %{{.*}}
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// CHECK: [[RESULT2:%[^ ]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{.*}}, <4 x float> %{{.*}}, <4 x float> [[RESULT]])
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// CHECK: fneg <4 x float> [[RESULT2]]
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vd = __builtin_vsx_xvnmsubadp(vd, vd, vd);
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// CHECK: [[RESULT:%[^ ]+]] = fneg <2 x double> %{{.*}}
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// CHECK: [[RESULT2:%[^ ]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x double> [[RESULT]])
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// CHECK: fneg <2 x double> [[RESULT2]]
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}
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@ -713,15 +713,15 @@ void test1() {
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/* vec_msub */
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res_vf = vec_msub(vf, vf, vf);
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// CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK: fneg <4 x float> %{{[0-9]+}}
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// CHECK-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
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// CHECK-LE: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK-LE: fneg <4 x float> %{{[0-9]+}}
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// CHECK-LE-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
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res_vd = vec_msub(vd, vd, vd);
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// CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
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// CHECK: fneg <2 x double> %{{[0-9]+}}
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// CHECK-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
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// CHECK-LE: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
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// CHECK-LE: fneg <2 x double> %{{[0-9]+}}
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// CHECK-LE-NEXT: call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
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res_vsll = vec_mul(vsll, vsll);
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@ -750,31 +750,31 @@ void test1() {
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res_vf = vec_nmadd(vf, vf, vf);
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// CHECK: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
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// CHECK-NEXT: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[FM]]
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// CHECK-NEXT: fneg <4 x float> %[[FM]]
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// CHECK-LE: [[FM:[0-9]+]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}})
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// CHECK-LE-NEXT: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[FM]]
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// CHECK-LE-NEXT: fneg <4 x float> %[[FM]]
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res_vd = vec_nmadd(vd, vd, vd);
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// CHECK: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
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// CHECK-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
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// CHECK-NEXT: fneg <2 x double> %[[FM]]
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// CHECK-LE: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}})
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// CHECK-LE-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
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// CHECK-LE-NEXT: fneg <2 x double> %[[FM]]
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res_vf = vec_nmsub(vf, vf, vf);
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// CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK: fneg <4 x float> %{{[0-9]+}}
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// CHECK-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
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// CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK-LE: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK: fneg <4 x float> %{{[0-9]+}}
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// CHECK-LE: fneg <4 x float> %{{[0-9]+}}
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// CHECK-LE-NEXT: call <4 x float> @llvm.fma.v4f32(<4 x float> %{{[0-9]+}}, <4 x float> %{{[0-9]+}}, <4 x float>
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// CHECK-LE: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
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// CHECK-LE: fneg <4 x float> %{{[0-9]+}}
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res_vd = vec_nmsub(vd, vd, vd);
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// CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
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// CHECK: fneg <2 x double> %{{[0-9]+}}
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// CHECK-NEXT: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
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// CHECK-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
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// CHECK-LE: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
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// CHECK-NEXT: fneg <2 x double> %[[FM]]
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// CHECK-LE: fneg <2 x double> %{{[0-9]+}}
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// CHECK-LE-NEXT: [[FM:[0-9]+]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %{{[0-9]+}}, <2 x double> %{{[0-9]+}}, <2 x double>
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// CHECK-LE-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
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// CHECK-LE-NEXT: fneg <2 x double> %[[FM]]
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/* vec_nor */
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res_vsll = vec_nor(vsll, vsll);
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