forked from OSchip/llvm-project
Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.
llvm-svn: 178032
This commit is contained in:
Jyotsna Verma
parent
8a51d8ea95
commit
15957b129f
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@ -446,38 +446,58 @@ def MUX_ii : ALU32_ii<(outs IntRegs:$dst), (ins PredRegs:$src1, s8Ext:$src2,
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s8ExtPred:$src2,
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s8ImmPred:$src3)))]>;
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// Shift halfword.
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let isPredicable = 1 in
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def ASLH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = aslh($src1)",
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[(set (i32 IntRegs:$dst), (shl 16, (i32 IntRegs:$src1)))]>;
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// ALU32 - aslh, asrh, sxtb, sxth, zxtb, zxth
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multiclass ALU32_2op_Pbase<string mnemonic, bit isNot, bit isPredNew> {
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let isPredicatedNew = isPredNew in
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def NAME : ALU32Inst<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
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") $dst = ")#mnemonic#"($src2)">,
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Requires<[HasV4T]>;
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}
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let isPredicable = 1 in
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def ASRH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = asrh($src1)",
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[(set (i32 IntRegs:$dst), (sra 16, (i32 IntRegs:$src1)))]>;
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multiclass ALU32_2op_Pred<string mnemonic, bit PredNot> {
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let isPredicatedFalse = PredNot in {
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defm _c#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 0>;
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// Predicate new
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defm _cdn#NAME : ALU32_2op_Pbase<mnemonic, PredNot, 1>;
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}
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}
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// Sign extend.
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let isPredicable = 1 in
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def SXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = sxtb($src1)",
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[(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i8))]>;
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let isPredicable = 1 in
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def SXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = sxth($src1)",
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[(set (i32 IntRegs:$dst), (sext_inreg (i32 IntRegs:$src1), i16))]>;
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// Zero extend.
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multiclass ALU32_2op_base<string mnemonic> {
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let BaseOpcode = mnemonic in {
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let isPredicable = 1, neverHasSideEffects = 1 in
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def ZXTB : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = zxtb($src1)",
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[]>;
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def NAME : ALU32Inst<(outs IntRegs:$dst),
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(ins IntRegs:$src1),
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"$dst = "#mnemonic#"($src1)">;
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let Predicates = [HasV4T], validSubTargets = HasV4SubT, isPredicated = 1,
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neverHasSideEffects = 1 in {
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defm Pt_V4 : ALU32_2op_Pred<mnemonic, 0>;
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defm NotPt_V4 : ALU32_2op_Pred<mnemonic, 1>;
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}
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}
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}
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defm ASLH : ALU32_2op_base<"aslh">, PredNewRel;
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defm ASRH : ALU32_2op_base<"asrh">, PredNewRel;
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defm SXTB : ALU32_2op_base<"sxtb">, PredNewRel;
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defm SXTH : ALU32_2op_base<"sxth">, PredNewRel;
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defm ZXTB : ALU32_2op_base<"zxtb">, PredNewRel;
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defm ZXTH : ALU32_2op_base<"zxth">, PredNewRel;
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def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
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(ASLH IntRegs:$src1)>;
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def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
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(ASRH IntRegs:$src1)>;
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def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
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(SXTB IntRegs:$src1)>;
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def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
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(SXTH IntRegs:$src1)>;
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let isPredicable = 1, neverHasSideEffects = 1 in
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def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
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"$dst = zxth($src1)",
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[]>;
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//===----------------------------------------------------------------------===//
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// ALU32/PERM -
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//===----------------------------------------------------------------------===//
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@ -95,164 +95,6 @@ def NumUsesBelowThresCONST32 : PatFrag<(ops node:$addr),
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//===----------------------------------------------------------------------===//
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// ALU32 +
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//===----------------------------------------------------------------------===//
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// Shift halfword.
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let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
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def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = aslh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = asrh($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Sign extend.
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let isPredicated = 1, neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
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def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = sxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = sxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Zero exten.
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let neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in {
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def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = zxtb($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) $dst = zxth($src2)",
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[]>,
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Requires<[HasV4T]>;
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}
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// Generate frame index addresses.
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let neverHasSideEffects = 1, isReMaterializable = 1,
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isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
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@ -0,0 +1,21 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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define i32 @foo(i32 %a, i32 %b) nounwind readnone {
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; CHECK: lsl
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; CHECK: aslh
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entry:
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%shl1 = shl i32 16, %a
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%shl2 = shl i32 %b, 16
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%ret = mul i32 %shl1, %shl2
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ret i32 %ret
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}
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define i32 @bar(i32 %a, i32 %b) nounwind readnone {
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; CHECK: asrh
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; CHECK: lsr
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entry:
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%shl1 = ashr i32 16, %a
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%shl2 = ashr i32 %b, 16
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%ret = mul i32 %shl1, %shl2
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ret i32 %ret
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}
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