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[AMDGPU][MC][GFX11] Support base+soffset+offset SMEM loads. 

Reviewed By: dp

Differential Revision: https://reviews.llvm.org/D126207
This commit is contained in:
Ivan Kosarev 2022-05-24 15:12:45 +01:00
parent e6e0eb3bc8
commit 1586e1dc95
3 changed files with 19 additions and 10 deletions
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21
llvm/lib/Target/AMDGPU/SMInstructions.td
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@ -1129,16 +1129,19 @@ class SMEM_Real_gfx11<bits<8> op, SM_Pseudo ps, string opName = ps.Mnemonic> :
!if(ps.has_offset, !cast<int>(SGPR_NULL_gfx11plus.HWEncoding), ?));
}
multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_gfx11 : SMEM_Real_gfx11<op, immPs, opName> {
let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
class SMEM_Real_Load_gfx11<bits<8> op, string ps, string opName, dag offsets> :
SMEM_Real_gfx11<op, !cast<SM_Pseudo>(ps), opName> {
RegisterClass BaseClass = !cast<SM_Load_Pseudo>(ps).BaseClass;
let InOperandList = !con((ins BaseClass:$sbase), offsets, (ins CPol:$cpol));
}
def _SGPR_gfx11 : SMEM_Real_gfx11<op, sgprPs, opName> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
}
def : MnemonicAlias<immPs.Mnemonic, opName>, Requires<[isGFX11Plus]>;
multiclass SM_Real_Loads_gfx11<bits<8> op, string ps, string opName> {
def _IMM_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_IMM", opName, (ins smem_offset:$offset)>;
def _SGPR_gfx11 : SMEM_Real_Load_gfx11<op, ps#"_SGPR", opName, (ins SReg_32:$soffset)>;
def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11<
op, ps#"_SGPR_IMM", opName, (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
def : MnemonicAlias<!cast<SM_Pseudo>(ps#"_IMM").Mnemonic, opName>,
Requires<[isGFX11Plus]>;
}
defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD", "s_load_b32">;

3
llvm/test/MC/AMDGPU/gfx11_asm_smem.s
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@ -41,6 +41,9 @@ s_load_b32 s5, s[2:3], m0
s_load_b32 s5, s[2:3], 0x0
// GFX11: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
s_load_b32 s5, s[2:3], s7 offset:0x12345
// GFX11: encoding: [0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e]
s_load_b32 s5, s[2:3], s0 glc
// GFX11: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]

3
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt
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@ -9848,6 +9848,9 @@
# GFX11: s_load_b32 s5, s[2:3], 0x1234 glc dlc ; encoding: [0x41,0x61,0x00,0xf4,0x34,0x12,0x00,0xf8]
0x41,0x61,0x00,0xf4,0x34,0x12,0x00,0xf8
# GFX11: s_load_b32 s5, s[2:3], s7 offset:0x12345 ; encoding: [0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e]
0x41,0x01,0x00,0xf4,0x45,0x23,0x01,0x0e
# GFX11: s_load_b32 s5, s[2:3], m0 ; encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa