forked from OSchip/llvm-project
RISCV: handle 64-bit PCREL data relocations
We would previously fail to handle 64-bit PC-relative relocations on RISCV. This was exposed by trying to build with `-fprofile-instr-generate`. The original changes restricted the relocation handling to the text segment as the paired relocations are undesirable in at least the debug and .eh_frame sections. We now make this explicit to handle the general case for the data relocations as well. It would be preferable to use `R_RISCV_n_PCREL` when available to avoid an extra relocation. Differential Revision: https://reviews.llvm.org/D127549 Reviewed By: luismarques, MaskRay Fixes: #55971
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@ -207,6 +207,10 @@ class RISCVELFStreamer : public MCELFStreamer {
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static bool requiresFixups(MCContext &C, const MCExpr *Value,
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const MCExpr *&LHS, const MCExpr *&RHS) {
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auto IsMetadataOrEHFrameSection = [](const MCSection &S) -> bool {
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return S.getKind().isMetadata() || S.getName() == ".eh_frame";
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};
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const auto *MBE = dyn_cast<MCBinaryExpr>(Value);
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if (MBE == nullptr)
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return false;
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@ -225,10 +229,15 @@ class RISCVELFStreamer : public MCELFStreamer {
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MCConstantExpr::create(E.getConstant(), C), C);
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RHS = E.getSymB();
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return (A.isInSection() ? A.getSection().hasInstructions()
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: !A.getName().empty()) ||
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(B.isInSection() ? B.getSection().hasInstructions()
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: !B.getName().empty());
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// TODO: when available, R_RISCV_n_PCREL should be preferred.
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// Avoid pairwise relocations for symbolic difference in debug and .eh_frame
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if (A.isInSection())
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return !IsMetadataOrEHFrameSection(A.getSection());
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if (B.isInSection())
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return !IsMetadataOrEHFrameSection(B.getSection());
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// as well as for absolute symbols.
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return !A.getName().empty() || !B.getName().empty();
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}
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void reset() override {
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@ -0,0 +1,37 @@
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# RUN: llvm-mc -triple riscv64-unknown-linux-gnu -filetype obj -o - %s \
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# RUN: | llvm-readobj -r - | FileCheck %s
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# CHECK: Relocations [
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# CHECK: .relasx {
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# CHECK-NEXT: 0x0 R_RISCV_ADD64 y 0x0
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# CHECK-NEXT: 0x0 R_RISCV_SUB64 x 0x0
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# CHECK: }
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# CHECK: .relasy {
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# CHECK-NEXT: 0x0 R_RISCV_ADD64 x 0x0
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# CHECK-NEXT: 0x0 R_RISCV_SUB64 y 0x0
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# CHECK: }
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# CHECK: .relasz {
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# CHECK-NEXT: 0x0 R_RISCV_ADD64 z 0x0
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# CHECK-NEXT: 0x0 R_RISCV_SUB64 a 0x0
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# CHECK: }
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# CHECK: .relasa {
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# CHECK-NEXT: 0x0 R_RISCV_ADD64 a 0x0
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# CHECK-NEXT: 0x0 R_RISCV_SUB64 z 0x0
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# CHECK: }
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# CHECK: ]
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.section sx,"aw",@progbits
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x:
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.quad y-x
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.section sy,"aw",@progbits
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y:
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.quad x-y
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.section sz
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z:
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.quad z-a
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.section sa
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a:
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.quad a-z
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