forked from OSchip/llvm-project
AVX-512: Implemented missing encoding for FMA scalar instructions
Added tests for encoding Differential Revision: http://reviews.llvm.org/D10865 llvm-svn: 241159
This commit is contained in:
Igor Breger
parent
a06d258530
commit
15820b072b
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@ -274,6 +274,16 @@ multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
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multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag NonTiedIns, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS> :
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AVX512_maskable_common<O, F, _, Outs,
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!con((ins _.RC:$src1), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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!con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
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multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins,
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@ -4205,44 +4215,95 @@ defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubR
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// Scalar FMA
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, ValueType OpVT,
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X86MemOperand x86memop, Operand memop,
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PatFrag mem_frag> {
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let isCommutable = 1 in
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def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
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let mayLoad = 1 in
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def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, f128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(mem_frag addr:$src3))))]>;
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}
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} // Constraints = "$src1 = $dst"
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multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
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dag RHS_r, dag RHS_m > {
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defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
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defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
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f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
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defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
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f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
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let mayLoad = 1 in
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defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
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defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
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AVX512FMA3Base, EVEX_B, EVEX_RC;
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let isCodeGenOnly = 1 in {
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def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[RHS_r]>;
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let mayLoad = 1 in
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def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
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(ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[RHS_m]>;
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}// isCodeGenOnly = 1
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}
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}// Constraints = "$src1 = $dst"
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multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
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string SUFF> {
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defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
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(_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
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(_.VT (OpNode _.RC:$src2, _.RC:$src1,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
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(_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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_.FRC:$src3))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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(_.ScalarLdFrag addr:$src3))))>;
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defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
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(_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
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(_.VT (OpNode _.RC:$src2,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
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_.RC:$src1)),
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(_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
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_.FRC:$src1))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
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(_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
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defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
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(_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
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(_.VT (OpNode _.RC:$src1,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
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_.RC:$src2)),
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(_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
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_.FRC:$src2))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
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(_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
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}
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multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
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let Predicates = [HasAVX512] in {
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defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
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OpNodeRnd, f32x_info, "SS">,
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EVEX_CD8<32, CD8VT1>, VEX_LIG;
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defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
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OpNodeRnd, f64x_info, "SD">,
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EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
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}
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}
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defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
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defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
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defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
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defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
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//===----------------------------------------------------------------------===//
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// AVX-512 Scalar convert from sign integer to float/double
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@ -59,12 +59,41 @@ define <8 x double> @test_x86_fmsub_pd_z(<8 x double> %a0, <8 x double> %a1, <8
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ret <8 x double> %res
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}
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define double @test_x86_fmsub_sd_z(double %a0, double %a1, double %a2) {
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define double @test_x86_fmsub_213(double %a0, double %a1, double %a2) {
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; CHECK-LABEL: test_x86_fmsub_213:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vfmsub213sd %xmm2, %xmm0, %xmm1
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%x = fmul double %a0, %a1
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%res = fsub double %x, %a2
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ret double %res
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}
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define double @test_x86_fmsub_213_m(double %a0, double %a1, double * %a2_ptr) {
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; CHECK-LABEL: test_x86_fmsub_213_m:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vfmsub213sd (%rdi), %xmm0, %xmm1
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%a2 = load double , double *%a2_ptr
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%x = fmul double %a0, %a1
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%res = fsub double %x, %a2
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ret double %res
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}
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define double @test_x86_fmsub_231_m(double %a0, double %a1, double * %a2_ptr) {
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; CHECK-LABEL: test_x86_fmsub_231_m:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vfmsub231sd (%rdi), %xmm0, %xmm1
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; CHECK-NEXT: vmovaps %zmm1, %zmm0
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; CHECK-NEXT: retq
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%a2 = load double , double *%a2_ptr
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%x = fmul double %a0, %a2
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%res = fsub double %x, %a1
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ret double %res
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}
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define <16 x float> @test231_br(<16 x float> %a1, <16 x float> %a2) nounwind {
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; CHECK-LABEL: test231_br:
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; CHECK: ## BB#0:
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