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Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers 

clobbered by a call.

llvm-svn: 36448
This commit is contained in:
Bill Wendling 2007-04-25 21:31:48 +00:00
parent 0fbe14ab87
commit 157d7ee7e5
2 changed files with 2 additions and 1 deletions
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2
llvm/lib/Target/X86/X86.td
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@ -64,7 +64,7 @@ def : Proc<"prescott", [FeatureMMX, FeatureSSE1, FeatureSSE2,
def : Proc<"nocona", [FeatureMMX, FeatureSSE1, FeatureSSE2,
FeatureSSE3, Feature64Bit]>;
def : Proc<"core2", [FeatureMMX, FeatureSSE1, FeatureSSE2,
FeatureSSE3, Feature64Bit]>;
FeatureSSE3, FeatureSSSE3, Feature64Bit]>;
def : Proc<"k6", [FeatureMMX]>;
def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;

1
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -458,6 +458,7 @@ def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
let isCall = 1, noResults = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
"call ${dst:call}", []>;