forked from OSchip/llvm-project
[PowerPC] Improvements for BUILD_VECTOR Vol. 4
This is the final patch in the series of patches that improves BUILD_VECTOR handling on PowerPC. This adds a few peephole optimizations to remove redundant instructions. It also adds a large test case which encompasses a large set of code patterns that build vectors - this test case was the motivator for this series of patches. Differential Revision: https://reviews.llvm.org/D26066 llvm-svn: 288800
This commit is contained in:
Nemanja Ivanovic
parent
bfd5ff155a
commit
15748f4921
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@ -844,19 +844,9 @@ let Uses = [RM] in {
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def XXPERMDI : XX3Form_2<60, 10,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM),
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"xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, []>;
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let isCodeGenOnly = 1 in {
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def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA, u2imm:$DM),
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let isCodeGenOnly = 1 in
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def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
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"xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
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let D = 0 in
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def XXSPLTD0s : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA),
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"xxspltd $XT, $XA, 0", IIC_VecPerm, []>;
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let D = 1 in
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def XXSPLTD1s : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA),
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"xxspltd $XT, $XA, 1", IIC_VecPerm, []>;
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let D = 2 in
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def XXSWAPDs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vfrc:$XA),
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"xxswapd $XT, $XA", IIC_VecPerm, []>;
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}
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def XXSEL : XX4Form<60, 3,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
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"xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
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@ -928,6 +918,12 @@ def : InstAlias<"xxmrgld $XT, $XA, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3)>;
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def : InstAlias<"xxswapd $XT, $XB",
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(XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2)>;
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def : InstAlias<"xxspltd $XT, $XB, 0",
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(XXPERMDIs vsrc:$XT, vsfrc:$XB, 0)>;
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def : InstAlias<"xxspltd $XT, $XB, 1",
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(XXPERMDIs vsrc:$XT, vsfrc:$XB, 3)>;
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def : InstAlias<"xxswapd $XT, $XB",
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(XXPERMDIs vsrc:$XT, vsfrc:$XB, 2)>;
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let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
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@ -2510,11 +2506,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(v4i32 (scalar_to_vector ScalarLoads.ZELi8)),
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(v4i32 (XXSPLTWs (LXSIBZX xoaddr:$src), 1))>;
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def : Pat<(v2i64 (scalar_to_vector ScalarLoads.ZELi8i64)),
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(v2i64 (XXSPLTD0s (LXSIBZX xoaddr:$src)))>;
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(v2i64 (XXPERMDIs (LXSIBZX xoaddr:$src), 0))>;
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def : Pat<(v4i32 (scalar_to_vector ScalarLoads.SELi8)),
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(v4i32 (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1))>;
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def : Pat<(v2i64 (scalar_to_vector ScalarLoads.SELi8i64)),
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(v2i64 (XXSPLTD0s (VEXTSB2Ds (LXSIBZX xoaddr:$src))))>;
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(v2i64 (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0))>;
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// Build vectors from i16 loads
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def : Pat<(v8i16 (scalar_to_vector ScalarLoads.Li16)),
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@ -2522,11 +2518,11 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(v4i32 (scalar_to_vector ScalarLoads.ZELi16)),
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(v4i32 (XXSPLTWs (LXSIHZX xoaddr:$src), 1))>;
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def : Pat<(v2i64 (scalar_to_vector ScalarLoads.ZELi16i64)),
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(v2i64 (XXSPLTD0s (LXSIHZX xoaddr:$src)))>;
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(v2i64 (XXPERMDIs (LXSIHZX xoaddr:$src), 0))>;
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def : Pat<(v4i32 (scalar_to_vector ScalarLoads.SELi16)),
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(v4i32 (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1))>;
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def : Pat<(v2i64 (scalar_to_vector ScalarLoads.SELi16i64)),
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(v2i64 (XXSPLTD0s (VEXTSH2Ds (LXSIHZX xoaddr:$src))))>;
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(v2i64 (XXPERMDIs (VEXTSH2Ds (LXSIHZX xoaddr:$src)), 0))>;
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let Predicates = [IsBigEndian, HasP9Vector] in {
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// Scalar stores of i8
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@ -2760,9 +2756,11 @@ let AddedComplexity = 400 in {
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// Build vectors of floating point converted to i64.
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def : Pat<(v2i64 (build_vector FltToLong.A, FltToLong.A)),
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(v2i64 (XXPERMDIs (COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
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(v2i64 (XXPERMDIs
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(COPY_TO_REGCLASS (XSCVDPSXDSs $A), VSFRC), 0))>;
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def : Pat<(v2i64 (build_vector FltToULong.A, FltToULong.A)),
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(v2i64 (XXPERMDIs (COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
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(v2i64 (XXPERMDIs
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(COPY_TO_REGCLASS (XSCVDPUXDSs $A), VSFRC), 0))>;
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def : Pat<(v2i64 (scalar_to_vector DblToLongLoad.A)),
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(v2i64 (XVCVDPSXDS (LXVDSX xoaddr:$A)))>;
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def : Pat<(v2i64 (scalar_to_vector DblToULongLoad.A)),
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@ -124,10 +124,40 @@ bool PPCMIPeephole::simplifyCode(void) {
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if (TrueReg1 == TrueReg2
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&& TargetRegisterInfo::isVirtualRegister(TrueReg1)) {
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
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unsigned DefOpc = DefMI ? DefMI->getOpcode() : 0;
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// If this is a splat fed by a splatting load, the splat is
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// redundant. Replace with a copy. This doesn't happen directly due
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// to code in PPCDAGToDAGISel.cpp, but it can happen when converting
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// a load of a double to a vector of 64-bit integers.
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auto isConversionOfLoadAndSplat = [=]() -> bool {
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if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
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return false;
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unsigned DefReg = lookThruCopyLike(DefMI->getOperand(1).getReg());
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if (TargetRegisterInfo::isVirtualRegister(DefReg)) {
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MachineInstr *LoadMI = MRI->getVRegDef(DefReg);
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if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
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return true;
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}
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return false;
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};
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if (DefMI && (Immed == 0 || Immed == 3)) {
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if (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat()) {
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DEBUG(dbgs()
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<< "Optimizing load-and-splat/splat "
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"to load-and-splat/copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(),
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TII->get(PPC::COPY), MI.getOperand(0).getReg())
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.addOperand(MI.getOperand(1));
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ToErase = &MI;
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Simplified = true;
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}
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}
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// If this is a splat or a swap fed by another splat, we
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// can replace it with a copy.
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if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
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if (DefOpc == PPC::XXPERMDI) {
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unsigned FeedImmed = DefMI->getOperand(3).getImm();
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unsigned FeedReg1
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= lookThruCopyLike(DefMI->getOperand(1).getReg());
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@ -170,8 +200,9 @@ bool PPCMIPeephole::simplifyCode(void) {
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ToErase = &MI;
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Simplified = true;
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}
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} else if ((Immed == 0 || Immed == 3) &&
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DefMI && DefMI->getOpcode() == PPC::XXPERMDIs) {
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} else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs &&
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(DefMI->getOperand(2).getImm() == 0 ||
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DefMI->getOperand(2).getImm() == 3)) {
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// Splat fed by another splat - switch the output of the first
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// and remove the second.
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DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
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@ -190,17 +221,32 @@ bool PPCMIPeephole::simplifyCode(void) {
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unsigned MyOpcode = MI.getOpcode();
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unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
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unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
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break;
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
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if (!DefMI)
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break;
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unsigned DefOpcode = DefMI->getOpcode();
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bool SameOpcode = (MyOpcode == DefOpcode) ||
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auto isConvertOfSplat = [=]() -> bool {
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if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
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return false;
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unsigned ConvReg = DefMI->getOperand(1).getReg();
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if (!TargetRegisterInfo::isVirtualRegister(ConvReg))
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return false;
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MachineInstr *Splt = MRI->getVRegDef(ConvReg);
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return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
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Splt->getOpcode() == PPC::XXSPLTW);
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};
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bool AlreadySplat = (MyOpcode == DefOpcode) ||
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(MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
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(MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs);
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// Splat fed by another splat - switch the output of the first
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// and remove the second.
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if (SameOpcode) {
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
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(MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
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(MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
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// If the instruction[s] that feed this splat have already splat
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// the value, this splat is redundant.
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if (AlreadySplat) {
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DEBUG(dbgs() << "Changing redundant splat to a copy: ");
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DEBUG(MI.dump());
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BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
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@ -234,9 +280,64 @@ bool PPCMIPeephole::simplifyCode(void) {
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}
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break;
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}
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case PPC::XVCVDPSP: {
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// If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
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unsigned TrueReg = lookThruCopyLike(MI.getOperand(1).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(TrueReg))
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break;
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MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
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// This can occur when building a vector of single precision or integer
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// values.
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if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
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unsigned DefsReg1 = lookThruCopyLike(DefMI->getOperand(1).getReg());
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unsigned DefsReg2 = lookThruCopyLike(DefMI->getOperand(2).getReg());
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if (!TargetRegisterInfo::isVirtualRegister(DefsReg1) ||
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!TargetRegisterInfo::isVirtualRegister(DefsReg2))
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break;
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MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
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MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
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if (!P1 || !P2)
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break;
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// Remove the passed FRSP instruction if it only feeds this MI and
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// set any uses of that FRSP (in this MI) to the source of the FRSP.
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auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
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if (RoundInstr->getOpcode() == PPC::FRSP &&
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MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
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Simplified = true;
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unsigned ConvReg1 = RoundInstr->getOperand(1).getReg();
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unsigned FRSPDefines = RoundInstr->getOperand(0).getReg();
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MachineInstr &Use = *(MRI->use_instr_begin(FRSPDefines));
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for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
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if (Use.getOperand(i).isReg() &&
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Use.getOperand(i).getReg() == FRSPDefines)
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Use.getOperand(i).setReg(ConvReg1);
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DEBUG(dbgs() << "Removing redundant FRSP:\n");
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DEBUG(RoundInstr->dump());
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DEBUG(dbgs() << "As it feeds instruction:\n");
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DEBUG(MI.dump());
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DEBUG(dbgs() << "Through instruction:\n");
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DEBUG(DefMI->dump());
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RoundInstr->eraseFromParent();
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}
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};
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// If the input to XVCVDPSP is a vector that was built (even
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// partially) out of FRSP's, the FRSP(s) can safely be removed
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// since this instruction performs the same operation.
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if (P1 != P2) {
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removeFRSPIfPossible(P1);
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removeFRSPIfPossible(P2);
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break;
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}
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removeFRSPIfPossible(P1);
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}
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break;
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}
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}
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}
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// If the last instruction was marked for elimination,
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// remove it now.
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if (ToErase) {
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File diff suppressed because it is too large
Load Diff
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@ -156,14 +156,10 @@ define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test14
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; CHECK: lwz [[LD:[0-9]+]],
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; FIXME: mtvsrws 34, [[LD]]
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; CHECK: mtvsrws [[SPLT:[0-9]+]], [[LD]]
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; CHECK: xxspltw 34, [[SPLT]], 3
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; CHECK: mtvsrws 34, [[LD]]
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; CHECK-BE-LABEL: test14
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; CHECK-BE: lwz [[LD:[0-9]+]],
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; FIXME: mtvsrws 34, [[LD]]
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; CHECK-BE: mtvsrws [[SPLT:[0-9]+]], [[LD]]
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; CHECK-BE: xxspltw 34, [[SPLT]], 0
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; CHECK-BE: mtvsrws 34, [[LD]]
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%0 = load i32, i32* %b, align 4
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%splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
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%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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@ -57,11 +57,11 @@ entry:
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%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %splat.splat
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; CHECK-LABEL: veculuc
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; CHECK: lxsibzx 34, 0, 3
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; CHECK-NEXT: xxspltd 34, 34, 0
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; CHECK: lxsibzx 0, 0, 3
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; CHECK-NEXT: xxspltd 34, 0, 0
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; CHECK-BE-LABEL: veculuc
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; CHECK-BE: lxsibzx 34, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 34, 0
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; CHECK-BE: lxsibzx 0, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 0, 0
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}
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; Function Attrs: norecurse nounwind readonly
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@ -120,11 +120,11 @@ entry:
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%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %splat.splat
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; CHECK-LABEL: vecsluc
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; CHECK: lxsibzx 34, 0, 3
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; CHECK-NEXT: xxspltd 34, 34, 0
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; CHECK: lxsibzx 0, 0, 3
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; CHECK-NEXT: xxspltd 34, 0, 0
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; CHECK-BE-LABEL: vecsluc
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; CHECK-BE: lxsibzx 34, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 34, 0
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; CHECK-BE: lxsibzx 0, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 0, 0
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}
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; Function Attrs: norecurse nounwind readonly
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@ -366,11 +366,11 @@ entry:
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%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %splat.splat
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; CHECK-LABEL: veculus
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; CHECK: lxsihzx 34, 0, 3
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; CHECK-NEXT: xxspltd 34, 34, 0
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; CHECK: lxsihzx 0, 0, 3
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; CHECK-NEXT: xxspltd 34, 0, 0
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; CHECK-BE-LABEL: veculus
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; CHECK-BE: lxsihzx 34, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 34, 0
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; CHECK-BE: lxsihzx 0, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 0, 0
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}
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; Function Attrs: norecurse nounwind readonly
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@ -430,11 +430,11 @@ entry:
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%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
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ret <2 x i64> %splat.splat
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; CHECK-LABEL: vecslus
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; CHECK: lxsihzx 34, 0, 3
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; CHECK-NEXT: xxspltd 34, 34, 0
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; CHECK: lxsihzx 0, 0, 3
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; CHECK-NEXT: xxspltd 34, 0, 0
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; CHECK-BE-LABEL: vecslus
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; CHECK-BE: lxsihzx 34, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 34, 0
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; CHECK-BE: lxsihzx 0, 0, 3
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; CHECK-BE-NEXT: xxspltd 34, 0, 0
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}
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; Function Attrs: norecurse nounwind readonly
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