forked from OSchip/llvm-project
Fix some serious bugs in the cmov descriptions, which didn't cause a problem because
we never generated them Make indentation a bit more consistent llvm-svn: 12549
This commit is contained in:
Chris Lattner
parent
ef327be6ed
commit
1563983d81
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@ -293,15 +293,15 @@ def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX
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let isTwoAddress = 1 in {
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// Conditional moves
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def CMOVB16rr : I <"cmove", 0x42, MRMSrcReg>, TB, OpSize; // if <u, R16 = R16
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def CMOVB16rm : Im16<"cmove", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
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def CMOVB32rr : I <"cmove", 0x42, MRMSrcReg>, TB; // if <u, R32 = R32
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def CMOVB32rm : Im32<"cmove", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
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def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if <u, R16 = R16
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def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
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def CMOVB32rr : I <"cmovb", 0x42, MRMSrcReg>, TB; // if <u, R32 = R32
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def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
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def CMOVAE16rr: I <"cmove", 0x43, MRMSrcReg>, TB, OpSize; // if >=u, R16 = R16
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def CMOVAE16rm: Im16<"cmove", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
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def CMOVAE32rr: I <"cmove", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32
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def CMOVAE32rm: Im32<"cmove", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
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def CMOVAE16rr: I <"cmovae", 0x43, MRMSrcReg>, TB, OpSize; // if >=u, R16 = R16
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def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
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def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32
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def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
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def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
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def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
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@ -313,45 +313,45 @@ def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16
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def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
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def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
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def CMOVBE16rr: I <"cmovne",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16
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def CMOVBE16rm: Im16<"cmovne",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
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def CMOVBE32rr: I <"cmovne",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32
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def CMOVBE32rm: Im32<"cmovne",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
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def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16
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def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
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def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32
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def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
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def CMOVA16rr : I <"cmove", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16
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def CMOVA16rm : Im16<"cmove", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
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def CMOVA32rr : I <"cmove", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32
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def CMOVA32rm : Im32<"cmove", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
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def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16
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def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
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def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32
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def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
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def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16
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def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
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def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
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def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
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def CMOVNS16rr: I <"cmovs", 0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16
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def CMOVNS16rm: Im16<"cmovs", 0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
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def CMOVNS32rr: I <"cmovs", 0x49, MRMSrcReg>, TB; // if !signed, R32 = R32
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def CMOVNS32rm: Im32<"cmovs", 0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
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def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16
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def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
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def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32
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def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
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def CMOVL16rr : I <"cmove", 0x4C, MRMSrcReg>, TB, OpSize; // if <s, R16 = R16
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def CMOVL16rm : Im16<"cmove", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
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def CMOVL32rr : I <"cmove", 0x4C, MRMSrcReg>, TB; // if <s, R32 = R32
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def CMOVL32rm : Im32<"cmove", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
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def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if <s, R16 = R16
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def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
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def CMOVL32rr : I <"cmovl", 0x4C, MRMSrcReg>, TB; // if <s, R32 = R32
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def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
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def CMOVGE16rr: I <"cmove", 0x4D, MRMSrcReg>, TB, OpSize; // if >=s, R16 = R16
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def CMOVGE16rm: Im16<"cmove", 0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
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def CMOVGE32rr: I <"cmove", 0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32
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def CMOVGE32rm: Im32<"cmove", 0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
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def CMOVGE16rr: I <"cmovge",0x4D, MRMSrcReg>, TB, OpSize; // if >=s, R16 = R16
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def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
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def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32
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def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
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def CMOVLE16rr: I <"cmovne",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16
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def CMOVLE16rm: Im16<"cmovne",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
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def CMOVLE32rr: I <"cmovne",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32
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def CMOVLE32rm: Im32<"cmovne",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
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def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16
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def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
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def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32
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def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
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def CMOVG16rr : I <"cmove", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16
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def CMOVG16rm : Im16<"cmove", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
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def CMOVG32rr : I <"cmove", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32
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def CMOVG32rm : Im32<"cmove", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
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def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16
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def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
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def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32
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def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
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// unary instructions
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def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
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@ -397,8 +397,8 @@ def AND8ri : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R
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def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
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def AND32ri : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>;
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def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
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def AND16mi : Im16i16 <"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
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def AND32mi : Im32i32 <"and", 0x81, MRM4m >; // [mem32] &= imm32
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def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
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def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32
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def AND16ri8 : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8
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def AND32ri8 : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8
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@ -420,8 +420,8 @@ def OR8ri : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R
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def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
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def OR32ri : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>;
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def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8
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def OR16mi : Im16i16 <"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
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def OR32mi : Im32i32 <"or" , 0x81, MRM1m >; // [mem32] |= imm32
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def OR16mi : Im16i16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16
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def OR32mi : Im32i32<"or" , 0x81, MRM1m >; // [mem32] |= imm32
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def OR16ri8 : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8
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def OR32ri8 : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8
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@ -443,8 +443,8 @@ def XOR8ri : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R
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def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
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def XOR32ri : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>;
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def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
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def XOR16mi : Im16i16 <"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
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def XOR32mi : Im32i32 <"xor", 0x81, MRM6m >; // [mem32] ^= R32
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def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
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def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
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def XOR16ri8 : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8
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def XOR32ri8 : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8
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@ -521,8 +521,8 @@ def ADD8ri : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus
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def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
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def ADD32ri : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>;
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def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
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def ADD16mi : Im16i16 <"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
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def ADD32mi : Im32i32 <"add", 0x81, MRM0m >; // [mem32] += I32
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def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
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def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32
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def ADD16ri8 : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm
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def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
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@ -548,8 +548,8 @@ def SUB8ri : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus
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def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
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def SUB32ri : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>;
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def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
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def SUB16mi : Im16i16 <"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
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def SUB32mi : Im32i32 <"sub", 0x81, MRM5m >; // [mem32] -= I32
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def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
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def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32
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def SUB16ri8 : Ii8 <"sub", 0x83, MRM5r >, OpSize;
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def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
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@ -572,8 +572,8 @@ def IMUL16rri : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16
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def IMUL32rri : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32
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def IMUL16rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8
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def IMUL32rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8
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def IMUL16rmi : Im16i16 <"imul", 0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
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def IMUL32rmi : Im32i32 <"imul", 0x69, MRMSrcMem>; // R32 = [mem32]*I32
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def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
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def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32
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def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
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def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
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