forked from OSchip/llvm-project
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
llvm-svn: 147344
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@ -483,12 +483,12 @@ class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern>
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: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
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Requires<[HasAES]>;
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Requires<[HasSSE2, HasAES]>;
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class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
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Requires<[HasAES]>;
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Requires<[HasSSE2, HasAES]>;
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// CLMUL Instruction Templates
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class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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