forked from OSchip/llvm-project
Revert "Enhance peephole optimization."
This reverts commit d84ca05ef7.
Will revert, update commit message and re-commit.
This commit is contained in:
Mingming Liu
parent
035aee725c
commit
1555c41abb
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@ -25,16 +25,13 @@
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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@ -967,101 +964,6 @@ inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
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return ShAmt < 4 && ShAmt > 0;
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}
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static bool findRedundantFlagInstr(MachineInstr &CmpInstr,
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MachineInstr &CmpValDefInstr,
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const MachineRegisterInfo *MRI,
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MachineInstr **AndInstr,
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const TargetRegisterInfo *TRI,
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bool &NoSignFlag, bool &ClearsOverflowFlag) {
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if (CmpValDefInstr.getOpcode() != X86::SUBREG_TO_REG)
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return false;
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if (CmpInstr.getOpcode() != X86::TEST64rr)
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return false;
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// CmpInstr is a TEST64rr instruction, and `X86InstrInfo::analyzeCompare`
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// guarantees that it's analyzable only if two registers are identical.
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assert(
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(CmpInstr.getOperand(0).getReg() == CmpInstr.getOperand(1).getReg()) &&
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"CmpInstr is an analyzable TEST64rr, and `X86InstrInfo::analyzeCompare` "
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"requires two reg operands are the same.");
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// Caller (`X86InstrInfo::optimizeCompareInstr`) guarantees that
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// `CmpValDefInstr` defines the value that's used by `CmpInstr`; in this case
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// if `CmpValDefInstr` sets the EFLAGS, it is likely that `CmpInstr` is
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// redundant.
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assert(
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(MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) &&
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"Caller guarantees that TEST64rr is a user of SUBREG_TO_REG.");
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// As seen in X86 td files, CmpValDefInstr.getOperand(1).getImm() is typically
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// 0.
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if (CmpValDefInstr.getOperand(1).getImm() != 0)
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return false;
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// As seen in X86 td files, CmpValDefInstr.getOperand(3) is typically
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// sub_32bit or sub_xmm.
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if (CmpValDefInstr.getOperand(3).getImm() != X86::sub_32bit)
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return false;
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MachineInstr *VregDefInstr =
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MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg());
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assert(VregDefInstr && "Must have a definition (SSA)");
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// Requires `CmpValDefInstr` and `VregDefInstr` are from the same MBB
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// to simplify the subsequent analysis.
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//
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// FIXME: If `VregDefInstr->getParent()` is the only predecessor of
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// `CmpValDefInstr.getParent()`, this could be handled.
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if (VregDefInstr->getParent() != CmpValDefInstr.getParent())
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return false;
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if (X86::isAND(VregDefInstr->getOpcode())) {
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// Get a sequence of instructions like
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// %reg = and* ... // Set EFLAGS
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// ... // EFLAGS not changed
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// %extended_reg = subreg_to_reg 0, %reg, %subreg.sub_32bit
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// test64rr %extended_reg, %extended_reg, implicit-def $eflags
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//
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// If subsequent readers use a subset of bits that don't change
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// after `and*` instructions, it's likely that the test64rr could
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// be optimized away.
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for (const MachineInstr &Instr :
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make_range(std::next(MachineBasicBlock::iterator(VregDefInstr)),
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MachineBasicBlock::iterator(CmpValDefInstr))) {
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// There are instructions between 'VregDefInstr' and
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// 'CmpValDefInstr' that modifies EFLAGS.
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if (Instr.modifiesRegister(X86::EFLAGS, TRI))
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return false;
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}
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*AndInstr = VregDefInstr;
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// AND instruction will essentially update SF and clear OF, so
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// NoSignFlag should be false in the sense that SF is modified by `AND`.
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//
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// However, the implementation artifically sets `NoSignFlag` to true
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// to poison the SF bit; that is to say, if SF is looked at later, the
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// optimization (to erase TEST64rr) will be disabled.
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//
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// The reason to poison SF bit is that SF bit value could be different
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// in the `AND` and `TEST` operation; signed bit is not known for `AND`,
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// and is known to be 0 as a result of `TEST64rr`.
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//
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// FIXME: As opposed to poisoning the SF bit direclty, consider peeking into
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// the AND instruction and using the static information to guide peephole optimization if possible.
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// For example, it's possible to fold a conditional move into a copy
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// if the relevant EFLAG bits could be deduced from an immediate operand of and operation.
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//
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NoSignFlag = true;
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// ClearsOverflowFlag is true for AND operation (no surprise).
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ClearsOverflowFlag = true;
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return true;
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}
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return false;
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}
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bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
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unsigned Opc, bool AllowSP, Register &NewSrc,
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bool &isKill, MachineOperand &ImplicitOp,
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@ -4324,23 +4226,6 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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MI = &Inst;
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break;
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}
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// Look back for the following pattern, in which case the test64rr
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// instruction could be erased.
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//
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// Example:
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// %reg = and32ri %in_reg, 5
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// ... // EFLAGS not changed.
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// %src_reg = subreg_to_reg 0, %reg, %subreg.sub_index
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// test64rr %src_reg, %src_reg, implicit-def $eflags
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MachineInstr *AndInstr = nullptr;
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if (IsCmpZero &&
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findRedundantFlagInstr(CmpInstr, Inst, MRI, &AndInstr, TRI,
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NoSignFlag, ClearsOverflowFlag)) {
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assert(AndInstr != nullptr && X86::isAND(AndInstr->getOpcode()));
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MI = AndInstr;
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break;
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}
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// Cannot find other candidates before definition of SrcReg.
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return false;
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}
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@ -1,196 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=x86_64-unknown-linux-gnu --run-pass=peephole-opt | FileCheck %s
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# Test that TEST64rr is erased in `test_erased`, and kept in `test_not_erased_when_sf_used`
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# and `test_not_erased_when_eflags_change`.
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--- |
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; ModuleID = 'tmp.ll'
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source_filename = "tmp.ll"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define i64 @test_erased(ptr %0, i64 %1, i64 %2) {
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%4 = load i64, ptr %0, align 8
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%5 = and i64 %4, 3
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%6 = icmp eq i64 %5, 0
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%7 = select i1 %6, i64 %1, i64 %5
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store i64 %7, ptr %0, align 8
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ret i64 %5
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}
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define i64 @test_not_erased_when_sf_used(ptr %0, i64 %1, i64 %2, i64 %3) {
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%5 = load i64, ptr %0, align 8
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%6 = and i64 %5, 3
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%7 = icmp slt i64 %6, 0
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%8 = select i1 %7, i64 %1, i64 %6
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store i64 %8, ptr %0, align 8
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ret i64 %5
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}
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define void @test_not_erased_when_eflags_change(ptr %0, i64 %1, i64 %2, i64 %3, ptr %4) {
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%6 = load i64, ptr %0, align 8
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%7 = and i64 %6, 3
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%8 = xor i64 %3, 5
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%9 = icmp eq i64 %7, 0
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%10 = select i1 %9, i64 %1, i64 %7
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store i64 %10, ptr %0, align 8
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store i64 %8, ptr %4, align 8
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ret void
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}
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...
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---
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name: test_erased
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alignment: 16
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr32, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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- { id: 6, class: gr64, preferred-register: '' }
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- { id: 7, class: gr64, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.3):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_erased
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
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; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def $eflags
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
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; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 4, implicit $eflags
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; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
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; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET 0, $rax
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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%3:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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%4:gr32 = COPY %3.sub_32bit
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%5:gr32 = AND32ri8 %4, 3, implicit-def dead $eflags
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%6:gr64 = SUBREG_TO_REG 0, killed %5, %subreg.sub_32bit
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TEST64rr %6, %6, implicit-def $eflags
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%7:gr64 = CMOV64rr %6, %1, 4, implicit $eflags
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MOV64mr %0, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.0)
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$rax = COPY %6
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RET 0, $rax
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...
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---
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name: test_not_erased_when_sf_used
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alignment: 16
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: gr32, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr64, preferred-register: '' }
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- { id: 8, class: gr64, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.4):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_not_erased_when_sf_used
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
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; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY2]], 3, implicit-def dead $eflags
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
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; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags
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; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY]], 8, implicit $eflags
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; CHECK-NEXT: MOV64mr [[COPY1]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
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; CHECK-NEXT: $rax = COPY [[MOV64rm]]
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; CHECK-NEXT: RET 0, $rax
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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%4:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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%5:gr32 = COPY %4.sub_32bit
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%6:gr32 = AND32ri8 %5, 3, implicit-def dead $eflags
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%7:gr64 = SUBREG_TO_REG 0, killed %6, %subreg.sub_32bit
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TEST64rr %7, %7, implicit-def $eflags
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%8:gr64 = CMOV64rr %7, %1, 8, implicit $eflags
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MOV64mr %0, 1, $noreg, 0, $noreg, killed %8 :: (store (s64) into %ir.0)
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$rax = COPY %4
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RET 0, $rax
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...
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---
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name: test_not_erased_when_eflags_change
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alignment: 16
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: gr64, preferred-register: '' }
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- { id: 1, class: gr64, preferred-register: '' }
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- { id: 2, class: gr64, preferred-register: '' }
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- { id: 3, class: gr64, preferred-register: '' }
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- { id: 4, class: gr64, preferred-register: '' }
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- { id: 5, class: gr64, preferred-register: '' }
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- { id: 6, class: gr32, preferred-register: '' }
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- { id: 7, class: gr32, preferred-register: '' }
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- { id: 8, class: gr64, preferred-register: '' }
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- { id: 9, class: gr64, preferred-register: '' }
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- { id: 10, class: gr64, preferred-register: '' }
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liveins:
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- { reg: '$rdi', virtual-reg: '%0' }
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- { reg: '$rsi', virtual-reg: '%1' }
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- { reg: '$rcx', virtual-reg: '%3' }
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- { reg: '$r8', virtual-reg: '%4' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.5):
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liveins: $rdi, $rsi, $rcx, $r8
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; CHECK-LABEL: name: test_not_erased_when_eflags_change
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $r8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rcx
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY3]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[MOV64rm]].sub_32bit
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; CHECK-NEXT: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY4]], 3, implicit-def dead $eflags
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[AND32ri8_]], %subreg.sub_32bit
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; CHECK-NEXT: [[XOR64ri8_:%[0-9]+]]:gr64 = XOR64ri8 [[COPY1]], 5, implicit-def dead $eflags
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; CHECK-NEXT: TEST64rr [[SUBREG_TO_REG]], [[SUBREG_TO_REG]], implicit-def $eflags
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; CHECK-NEXT: [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[SUBREG_TO_REG]], [[COPY2]], 4, implicit $eflags
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; CHECK-NEXT: MOV64mr [[COPY3]], 1, $noreg, 0, $noreg, killed [[CMOV64rr]] :: (store (s64) into %ir.0)
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; CHECK-NEXT: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, killed [[XOR64ri8_]] :: (store (s64) into %ir.4)
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; CHECK-NEXT: RET 0
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%4:gr64 = COPY $r8
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%3:gr64 = COPY $rcx
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%1:gr64 = COPY $rsi
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%0:gr64 = COPY $rdi
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%5:gr64 = MOV64rm %0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.0)
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%6:gr32 = COPY %5.sub_32bit
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%7:gr32 = AND32ri8 %6, 3, implicit-def dead $eflags
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%8:gr64 = SUBREG_TO_REG 0, killed %7, %subreg.sub_32bit
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%9:gr64 = XOR64ri8 %3, 5, implicit-def dead $eflags
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TEST64rr %8, %8, implicit-def $eflags
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%10:gr64 = CMOV64rr %8, %1, 4, implicit $eflags
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MOV64mr %0, 1, $noreg, 0, $noreg, killed %10 :: (store (s64) into %ir.0)
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MOV64mr %4, 1, $noreg, 0, $noreg, killed %9 :: (store (s64) into %ir.4)
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RET 0
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...
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