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Revert "[PPC64] Fix DQ-form instruction handling and emit error for misalign..." 

This reverts commit 5125b44dbb5d06b715213e4bec75c7346bfcc7d3.
ppc64-dq.s and ppc64-error-missaligned-dq.s fail on several of the build-bots.
Reverting to investigate.

llvm-svn: 340568
This commit is contained in:
Sean Fertile 2018-08-23 19:10:40 +00:00
parent 61d76eceed
commit 1542b0aef5
4 changed files with 7 additions and 119 deletions
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42
lld/ELF/Arch/PPC64.cpp
View File

@ -98,24 +98,6 @@ static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
static uint16_t highest(uint64_t V) { return V >> 48; } static uint16_t highest(uint64_t V) { return V >> 48; }
static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; } static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
// Extracts the 'PO' field of an instruction encoding.
static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
static bool isDQFormInstruction(uint32_t Encoding) {
switch (getPrimaryOpCode(Encoding)) {
default:
return false;
case 56:
// The only instruction with a primary opcode of 56 is `lq`.
return true;
case 61:
// There are both DS and DQ instruction forms with this primary opcode.
// Namely `lxv` and `stxv` are the DQ-forms that use it.
// The DS 'XO' bits being set to 01 is restricted to DQ form.
return (Encoding & 3) == 0x1;
}
}
PPC64::PPC64() { PPC64::PPC64() {
GotRel = R_PPC64_GLOB_DAT; GotRel = R_PPC64_GLOB_DAT;
PltRel = R_PPC64_JMP_SLOT; PltRel = R_PPC64_JMP_SLOT;
@ -316,7 +298,7 @@ void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
break; break;
} }
case R_PPC64_TLS: { case R_PPC64_TLS: {
uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc)); uint32_t PrimaryOp = (read32(Loc) & 0xFC000000) >> 26; // bits 0-5
if (PrimaryOp != 31) if (PrimaryOp != 31)
error("unrecognized instruction for IE to LE R_PPC64_TLS"); error("unrecognized instruction for IE to LE R_PPC64_TLS");
uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30 uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
@ -524,15 +506,10 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
write16(Loc, Val); write16(Loc, Val);
break; break;
case R_PPC64_ADDR16_DS: case R_PPC64_ADDR16_DS:
case R_PPC64_TPREL16_DS: { case R_PPC64_TPREL16_DS:
checkInt(Loc, Val, 16, Type); checkInt(Loc, Val, 16, Type);
// DQ-form instructions use bits 28-31 as part of the instruction encoding write16(Loc, (read16(Loc) & 3) | (Val & ~3));
// DS-form instructions only use bits 30-31. break;
uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
uint16_t Mask = isDQFormInstruction(read32(Loc - EndianOffset)) ? 0xF : 0x3;
checkAlignment(Loc, lo(Val), Mask + 1, Type);
write16(Loc, (read16(Loc) & Mask) | lo(Val));
} break;
case R_PPC64_ADDR16_HA: case R_PPC64_ADDR16_HA:
case R_PPC64_REL16_HA: case R_PPC64_REL16_HA:
case R_PPC64_TPREL16_HA: case R_PPC64_TPREL16_HA:
@ -565,14 +542,9 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
write16(Loc, lo(Val)); write16(Loc, lo(Val));
break; break;
case R_PPC64_ADDR16_LO_DS: case R_PPC64_ADDR16_LO_DS:
case R_PPC64_TPREL16_LO_DS: { case R_PPC64_TPREL16_LO_DS:
// DQ-form instructions use bits 28-31 as part of the instruction encoding write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3));
// DS-form instructions only use bits 30-31. break;
uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
uint16_t Mask = isDQFormInstruction(read32(Loc - EndianOffset)) ? 0xF : 0x3;
checkAlignment(Loc, lo(Val), Mask + 1, Type);
write16(Loc, (read16(Loc) & Mask) | lo(Val));
} break;
case R_PPC64_ADDR32: case R_PPC64_ADDR32:
case R_PPC64_REL32: case R_PPC64_REL32:
checkInt(Loc, Val, 32, Type); checkInt(Loc, Val, 32, Type);

32
lld/test/ELF/ppc64-dq.s
View File

@ -1,32 +0,0 @@
# REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -D %t | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
# RUN: ld.lld %t.o -o %t
# RUN: llvm-objdump -D %t | FileCheck %s
.global test
.p2align 4
.type test,@function
test:
.Lgep:
addis 2, 12, .TOC.-.Lgep@ha
addi 2, 2, .TOC.-.Lgep@l
.Llep:
.localentry test, .Llep-.Lgep
addis 3, 2, qword@toc@ha
lxv 3, qword@toc@l(3)
addis 3, 2, qword@toc@ha
stxv 3, qword@toc@l(3)
blr
.comm qword, 16, 16
# Verify that we don't overwrite any of the extended opcode bits on a DQ form
# instruction.
# CHECK-LABEL: test
# CHECK: lxv 3, -32768(3)
# CHECK: stxv 3, -32768(3)

26
lld/test/ELF/ppc64-error-missaligned-dq.s
View File

@ -1,26 +0,0 @@
# REQUIRES: ppc
#
# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 16 bytes
.global test
.p2align 4
.type test,@function
test:
.Lgep:
addis 2, 12, .TOC.-.Lgep@ha
addi 2, 2, .TOC.-.Lgep@l
.Llep:
.localentry test, .Llep-.Lgep
addis 3, 2, qword@toc@ha
lxv 3, qword@toc@l(3)
blr
.comm pad, 1, 1
.comm qword, 16, 1

26
lld/test/ELF/ppc64-error-missaligned-ds.s
View File

@ -1,26 +0,0 @@
# REQUIRES: ppc
# RUN: llvm-mc -filetype=obj -triple=powerpc64le-unknown-linux %s -o %t.o
# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux %s -o %t.o
# RUN: not ld.lld %t.o -o %t 2>&1 | FileCheck %s
# CHECK: improper alignment for relocation R_PPC64_ADDR16_LO_DS: 0x8001 is not aligned to 4 bytes
.global test
.p2align 4
.type test,@function
test:
.Lgep:
addis 2, 12, .TOC.-.Lgep@ha
addi 2, 2, .TOC.-.Lgep@l
.Llep:
.localentry test, .Llep-.Lgep
addis 3, 2, word@toc@ha
lwa 3, word@toc@l(3)
blr
.comm pad, 1, 1
.comm word, 4, 1