forked from OSchip/llvm-project
[MIPS GlobalISel] ClampScalar G_AND G_OR and G_XOR
Add narrowScalar for G_AND and G_XOR. Legalize G_AND G_OR and G_XOR for types other then s32 with clampScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D55362 llvm-svn: 349475
This commit is contained in:
Petar Avramovic
parent
307839cca9
commit
150fd430f6
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@ -578,7 +578,9 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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MI.eraseFromParent();
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return Legalized;
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}
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case TargetOpcode::G_OR: {
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case TargetOpcode::G_AND:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_XOR: {
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// Legalize bitwise operation:
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// A = BinOp<Ty> B, C
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// into:
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@ -617,7 +619,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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// Do the operation on each small part.
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for (int i = 0; i < NumParts; ++i)
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MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]);
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MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]},
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{SrcsReg1[i], SrcsReg2[i]});
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// Gather the destination registers into the final destination.
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unsigned DstReg = MI.getOperand(0).getReg();
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@ -34,7 +34,11 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder({G_LOAD, G_STORE})
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.legalForCartesianProduct({p0, s32}, {p0});
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR})
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getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
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.legalFor({s32})
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.clampScalar(0, s32, s32);
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getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
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.legalFor({s32});
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getActionDefinitionsBuilder(G_ICMP)
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@ -2,9 +2,9 @@
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @and(i32, i32) {entry: ret void}
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define void @or(i32, i32) {entry: ret void}
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define void @xor(i32, i32) {entry: ret void}
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define void @and_i32() {entry: ret void}
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define void @or_i32() {entry: ret void}
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define void @xor_i32() {entry: ret void}
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define void @shl(i32) {entry: ret void}
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define void @ashr(i32) {entry: ret void}
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define void @lshr(i32) {entry: ret void}
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@ -14,7 +14,7 @@
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...
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---
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name: and
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name: and_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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@ -23,7 +23,7 @@ body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and
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; MIPS32-LABEL: name: and_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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@ -38,7 +38,7 @@ body: |
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...
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---
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name: or
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name: or_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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@ -47,7 +47,7 @@ body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: or
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; MIPS32-LABEL: name: or_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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@ -62,7 +62,7 @@ body: |
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...
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---
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name: xor
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name: xor_i32
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alignment: 2
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legalized: true
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regBankSelected: true
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@ -71,7 +71,7 @@ body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: xor
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; MIPS32-LABEL: name: xor_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
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@ -1,48 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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define i32 @and(i32 %a, i32 %b) {
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; MIPS32-LABEL: name: and
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; MIPS32: bb.1.entry:
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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entry:
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%and = and i32 %b, %a
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ret i32 %and
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}
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define i32 @or(i32 %a, i32 %b) {
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; MIPS32-LABEL: name: or
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; MIPS32: bb.1.entry:
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[OR]](s32)
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; MIPS32: RetRA implicit $v0
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entry:
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%or = or i32 %b, %a
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ret i32 %or
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}
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define i32 @xor(i32 %a, i32 %b) {
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; MIPS32-LABEL: name: xor
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; MIPS32: bb.1.entry:
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
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; MIPS32: $v0 = COPY [[XOR]](s32)
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; MIPS32: RetRA implicit $v0
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entry:
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%xor = xor i32 %b, %a
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ret i32 %xor
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}
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define i32 @shl(i32 %a) {
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; MIPS32-LABEL: name: shl
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; MIPS32: bb.1.entry:
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@ -2,9 +2,21 @@
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @and(i32, i32) {entry: ret void}
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define void @or(i32, i32) {entry: ret void}
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define void @xor(i32, i32) {entry: ret void}
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define void @and_i1() {entry: ret void}
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define void @and_i8() {entry: ret void}
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define void @and_i16() {entry: ret void}
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define void @and_i32() {entry: ret void}
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define void @and_i64() {entry: ret void}
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define void @or_i1() {entry: ret void}
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define void @or_i8() {entry: ret void}
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define void @or_i16() {entry: ret void}
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define void @or_i32() {entry: ret void}
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define void @or_i64() {entry: ret void}
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define void @xor_i1() {entry: ret void}
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define void @xor_i8() {entry: ret void}
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define void @xor_i16() {entry: ret void}
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define void @xor_i32() {entry: ret void}
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define void @xor_i64() {entry: ret void}
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define void @shl(i32) {entry: ret void}
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define void @ashr(i32) {entry: ret void}
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define void @lshr(i32) {entry: ret void}
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@ -14,14 +26,98 @@
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...
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---
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name: and
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name: and_i1
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and
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; MIPS32-LABEL: name: and_i1
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s1) = G_TRUNC %3(s32)
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%4:_(s1) = G_AND %1, %0
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%5:_(s32) = G_ANYEXT %4(s1)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: and_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and_i8
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_AND %1, %0
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%5:_(s32) = G_ANYEXT %4(s8)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: and_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and_i16
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s16) = G_TRUNC %3(s32)
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%4:_(s16) = G_AND %1, %0
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%5:_(s32) = G_ANYEXT %4(s16)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: and_i32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: and_i32
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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@ -36,14 +132,130 @@ body: |
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...
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---
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name: or
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name: and_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1, $a2, $a3
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; MIPS32-LABEL: name: and_i64
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]]
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; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: $v1 = COPY [[AND1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%2:_(s32) = COPY $a0
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%3:_(s32) = COPY $a1
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%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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%4:_(s32) = COPY $a2
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%5:_(s32) = COPY $a3
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%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
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%6:_(s64) = G_AND %1, %0
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$v0 = COPY %7(s32)
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$v1 = COPY %8(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: or_i1
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: or
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; MIPS32-LABEL: name: or_i1
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s1) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s1) = G_TRUNC %3(s32)
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%4:_(s1) = G_OR %1, %0
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%5:_(s32) = G_ANYEXT %4(s1)
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$v0 = COPY %5(s32)
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RetRA implicit $v0
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...
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---
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name: or_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0, $a1
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; MIPS32-LABEL: name: or_i8
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; MIPS32: liveins: $a0, $a1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
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; MIPS32: $v0 = COPY [[COPY4]](s32)
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; MIPS32: RetRA implicit $v0
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%2:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %2(s32)
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%3:_(s32) = COPY $a1
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%1:_(s8) = G_TRUNC %3(s32)
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%4:_(s8) = G_OR %1, %0
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%5:_(s32) = G_ANYEXT %4(s8)
|
||||
$v0 = COPY %5(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: or_i16
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: or_i16
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
|
||||
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%2:_(s32) = COPY $a0
|
||||
%0:_(s16) = G_TRUNC %2(s32)
|
||||
%3:_(s32) = COPY $a1
|
||||
%1:_(s16) = G_TRUNC %3(s32)
|
||||
%4:_(s16) = G_OR %1, %0
|
||||
%5:_(s32) = G_ANYEXT %4(s16)
|
||||
$v0 = COPY %5(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: or_i32
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: or_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
|
|
@ -58,14 +270,130 @@ body: |
|
|||
|
||||
...
|
||||
---
|
||||
name: xor
|
||||
name: or_i64
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
|
||||
; MIPS32-LABEL: name: or_i64
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||||
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]]
|
||||
; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]]
|
||||
; MIPS32: $v0 = COPY [[OR]](s32)
|
||||
; MIPS32: $v1 = COPY [[OR1]](s32)
|
||||
; MIPS32: RetRA implicit $v0, implicit $v1
|
||||
%2:_(s32) = COPY $a0
|
||||
%3:_(s32) = COPY $a1
|
||||
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
|
||||
%4:_(s32) = COPY $a2
|
||||
%5:_(s32) = COPY $a3
|
||||
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
|
||||
%6:_(s64) = G_OR %1, %0
|
||||
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||||
$v0 = COPY %7(s32)
|
||||
$v1 = COPY %8(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
---
|
||||
name: xor_i1
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: xor
|
||||
; MIPS32-LABEL: name: xor_i1
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
|
||||
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%2:_(s32) = COPY $a0
|
||||
%0:_(s1) = G_TRUNC %2(s32)
|
||||
%3:_(s32) = COPY $a1
|
||||
%1:_(s1) = G_TRUNC %3(s32)
|
||||
%4:_(s1) = G_XOR %1, %0
|
||||
%5:_(s32) = G_ANYEXT %4(s1)
|
||||
$v0 = COPY %5(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: xor_i8
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: xor_i8
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
|
||||
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%2:_(s32) = COPY $a0
|
||||
%0:_(s8) = G_TRUNC %2(s32)
|
||||
%3:_(s32) = COPY $a1
|
||||
%1:_(s8) = G_TRUNC %3(s32)
|
||||
%4:_(s8) = G_XOR %1, %0
|
||||
%5:_(s32) = G_ANYEXT %4(s8)
|
||||
$v0 = COPY %5(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: xor_i16
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: xor_i16
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
||||
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
|
||||
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
|
||||
; MIPS32: $v0 = COPY [[COPY4]](s32)
|
||||
; MIPS32: RetRA implicit $v0
|
||||
%2:_(s32) = COPY $a0
|
||||
%0:_(s16) = G_TRUNC %2(s32)
|
||||
%3:_(s32) = COPY $a1
|
||||
%1:_(s16) = G_TRUNC %3(s32)
|
||||
%4:_(s16) = G_XOR %1, %0
|
||||
%5:_(s32) = G_ANYEXT %4(s16)
|
||||
$v0 = COPY %5(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: xor_i32
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: xor_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
|
|
@ -78,6 +406,38 @@ body: |
|
|||
$v0 = COPY %2(s32)
|
||||
RetRA implicit $v0
|
||||
|
||||
...
|
||||
---
|
||||
name: xor_i64
|
||||
alignment: 2
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.1.entry:
|
||||
liveins: $a0, $a1, $a2, $a3
|
||||
|
||||
; MIPS32-LABEL: name: xor_i64
|
||||
; MIPS32: liveins: $a0, $a1, $a2, $a3
|
||||
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
|
||||
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
|
||||
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
|
||||
; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]]
|
||||
; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]]
|
||||
; MIPS32: $v0 = COPY [[XOR]](s32)
|
||||
; MIPS32: $v1 = COPY [[XOR1]](s32)
|
||||
; MIPS32: RetRA implicit $v0, implicit $v1
|
||||
%2:_(s32) = COPY $a0
|
||||
%3:_(s32) = COPY $a1
|
||||
%0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
|
||||
%4:_(s32) = COPY $a2
|
||||
%5:_(s32) = COPY $a3
|
||||
%1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
|
||||
%6:_(s64) = G_XOR %1, %0
|
||||
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
||||
$v0 = COPY %7(s32)
|
||||
$v1 = COPY %8(s32)
|
||||
RetRA implicit $v0, implicit $v1
|
||||
|
||||
...
|
||||
---
|
||||
name: shl
|
||||
|
|
|
|||
|
|
@ -1,9 +1,41 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
|
||||
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
|
||||
|
||||
define i32 @and(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: and:
|
||||
define i1 @and_i1(i1 %a, i1 %b) {
|
||||
; MIPS32-LABEL: and_i1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: and $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%and = and i1 %b, %a
|
||||
ret i1 %and
|
||||
}
|
||||
|
||||
define i8 @and_i8(i8 %a, i8 %b) {
|
||||
; MIPS32-LABEL: and_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: and $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%and = and i8 %b, %a
|
||||
ret i8 %and
|
||||
}
|
||||
|
||||
define i16 @and_i16(i16 %a, i16 %b) {
|
||||
; MIPS32-LABEL: and_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: and $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%and = and i16 %b, %a
|
||||
ret i16 %and
|
||||
}
|
||||
|
||||
define i32 @and_i32(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: and_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: and $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
|
|
@ -13,8 +45,53 @@ entry:
|
|||
ret i32 %and
|
||||
}
|
||||
|
||||
define i32 @or(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: or:
|
||||
define i64 @and_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: and_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: and $2, $6, $4
|
||||
; MIPS32-NEXT: and $3, $7, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%and = and i64 %b, %a
|
||||
ret i64 %and
|
||||
}
|
||||
|
||||
define i1 @or_i1(i1 %a, i1 %b) {
|
||||
; MIPS32-LABEL: or_i1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: or $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%or = or i1 %b, %a
|
||||
ret i1 %or
|
||||
}
|
||||
|
||||
define i8 @or_i8(i8 %a, i8 %b) {
|
||||
; MIPS32-LABEL: or_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: or $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%or = or i8 %b, %a
|
||||
ret i8 %or
|
||||
}
|
||||
|
||||
define i16 @or_i16(i16 %a, i16 %b) {
|
||||
; MIPS32-LABEL: or_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: or $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%or = or i16 %b, %a
|
||||
ret i16 %or
|
||||
}
|
||||
|
||||
define i32 @or_i32(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: or_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: or $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
|
|
@ -24,8 +101,53 @@ entry:
|
|||
ret i32 %or
|
||||
}
|
||||
|
||||
define i32 @xor(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: xor:
|
||||
define i64 @or_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: or_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: or $2, $6, $4
|
||||
; MIPS32-NEXT: or $3, $7, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%or = or i64 %b, %a
|
||||
ret i64 %or
|
||||
}
|
||||
|
||||
define i1 @xor_i1(i1 %a, i1 %b) {
|
||||
; MIPS32-LABEL: xor_i1:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%xor = xor i1 %b, %a
|
||||
ret i1 %xor
|
||||
}
|
||||
|
||||
define i8 @xor_i8(i8 %a, i8 %b) {
|
||||
; MIPS32-LABEL: xor_i8:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%xor = xor i8 %b, %a
|
||||
ret i8 %xor
|
||||
}
|
||||
|
||||
define i16 @xor_i16(i16 %a, i16 %b) {
|
||||
; MIPS32-LABEL: xor_i16:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%xor = xor i16 %b, %a
|
||||
ret i16 %xor
|
||||
}
|
||||
|
||||
define i32 @xor_i32(i32 %a, i32 %b) {
|
||||
; MIPS32-LABEL: xor_i32:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $2, $5, $4
|
||||
; MIPS32-NEXT: jr $ra
|
||||
|
|
@ -35,6 +157,18 @@ entry:
|
|||
ret i32 %xor
|
||||
}
|
||||
|
||||
define i64 @xor_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-LABEL: xor_i64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
; MIPS32-NEXT: xor $2, $6, $4
|
||||
; MIPS32-NEXT: xor $3, $7, $5
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
entry:
|
||||
%xor = xor i64 %b, %a
|
||||
ret i64 %xor
|
||||
}
|
||||
|
||||
define i32 @shl(i32 %a) {
|
||||
; MIPS32-LABEL: shl:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@
|
|||
--- |
|
||||
|
||||
|
||||
define void @and(i32, i32) {entry: ret void}
|
||||
define void @or(i32, i32) {entry: ret void}
|
||||
define void @xor(i32, i32) {entry: ret void}
|
||||
define void @and_i32() {entry: ret void}
|
||||
define void @or_i32() {entry: ret void}
|
||||
define void @xor_i32() {entry: ret void}
|
||||
define void @shl(i32) {entry: ret void}
|
||||
define void @ashr(i32) {entry: ret void}
|
||||
define void @lshr(i32) {entry: ret void}
|
||||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
...
|
||||
---
|
||||
name: and
|
||||
name: and_i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
|
|
@ -23,7 +23,7 @@ body: |
|
|||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: and
|
||||
; MIPS32-LABEL: name: and_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
|
|
@ -38,7 +38,7 @@ body: |
|
|||
|
||||
...
|
||||
---
|
||||
name: or
|
||||
name: or_i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
|
|
@ -46,7 +46,7 @@ body: |
|
|||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: or
|
||||
; MIPS32-LABEL: name: or_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
|
|
@ -61,7 +61,7 @@ body: |
|
|||
|
||||
...
|
||||
---
|
||||
name: xor
|
||||
name: xor_i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
tracksRegLiveness: true
|
||||
|
|
@ -69,7 +69,7 @@ body: |
|
|||
bb.1.entry:
|
||||
liveins: $a0, $a1
|
||||
|
||||
; MIPS32-LABEL: name: xor
|
||||
; MIPS32-LABEL: name: xor_i32
|
||||
; MIPS32: liveins: $a0, $a1
|
||||
; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
|
||||
; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1
|
||||
|
|
|
|||
Loading…
Reference in New Issue