forked from OSchip/llvm-project
[X86][Btver2] Add support for multiple pipelines stages for x86 scalar schedules. NFCI.
This allows us to use JWriteResIntPair for complex schedule classes (like WriteIDiv) as well as single pipe instructions. llvm-svn: 327686
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@ -72,20 +72,20 @@ def : ReadAdvance<ReadAfterLd, 3>;
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat, int Res = 1, int UOps = 1> {
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [1], int UOps = 1> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> {
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = [Res];
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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let Latency = !add(Lat, 3);
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let ResourceCycles = [1, Res];
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let ResourceCycles = !listconcat([1], Res);
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let NumMicroOps = UOps;
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}
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}
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@ -116,26 +116,15 @@ def : WriteRes<WriteRMW, [JSAGU]>;
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// Arithmetic.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteALU, JALU01, 1>;
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defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
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defm : JWriteResIntPair<WriteALU, [JALU01], 1>;
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defm : JWriteResIntPair<WriteIMul, [JALU1], 3>;
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defm : JWriteResIntPair<WriteIDiv, [JALU1, JDiv], 41, [1, 41], 2>; // Worst case (i64 division)
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def : WriteRes<WriteIMulH, [JALU1]> {
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let Latency = 6;
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let ResourceCycles = [4];
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}
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// Worst case (i64 division)
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def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
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let Latency = 41;
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let ResourceCycles = [1, 41];
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let NumMicroOps = 2;
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}
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def : WriteRes<WriteIDivLd, [JLAGU, JALU1, JDiv]> {
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let Latency = 44;
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let ResourceCycles = [1, 1, 41];
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let NumMicroOps = 2;
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}
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// This is for simple LEAs with one or two input operands.
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// FIXME: SAGU 3-operand LEA
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def : WriteRes<WriteLEA, [JALU01]>;
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@ -181,7 +170,7 @@ def : InstRW<[JWriteIDiv32Ld], (instrs DIV32m, IDIV32m)>;
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// Integer shifts and rotates.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteShift, JALU01, 1>;
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defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
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def JWriteSHLDrri : SchedWriteRes<[JALU01]> {
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let Latency = 3;
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@ -232,7 +221,7 @@ def : WriteRes<WriteZero, []>;
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// consume resources. Indirect branches can fold loads.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteJump, JALU01, 1>;
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defm : JWriteResIntPair<WriteJump, [JALU01], 1>;
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////////////////////////////////////////////////////////////////////////////////
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// Special case scheduling classes.
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