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AMDGPU/GlobalISel: RegBankSelect for amdgcn.class 

llvm-svn: 364214
This commit is contained in:
Matt Arsenault 2019-06-24 18:00:47 +00:00
parent 318b6dafca
commit 14d0b646b7
2 changed files with 40 additions and 0 deletions
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9
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -1502,6 +1502,15 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
break;
}
case Intrinsic::amdgcn_class: {
unsigned SrcReg = MI.getOperand(2).getReg();
unsigned SrcSize = MRI.getType(SrcReg).getSizeInBits();
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize);
OpdsMapping[2] = AMDGPU::getValueMapping(getRegBankID(SrcReg, MRI, *TRI),
SrcSize);
break;
}
}
break;
}

31
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir Normal file
View File

@ -0,0 +1,31 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: class_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: class_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
%0:_(s32) = COPY $sgpr0
%1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
...
---
name: class_v
legalized: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: class_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[COPY]](s32), 1
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, 1
...