forked from OSchip/llvm-project
Initial support for copy elimination by commuting its definition MI.
PR1877.
A3 = op A2 B0<kill>
...
B1 = A3 <- this copy
...
= op A3 <- more uses
==>
B2 = op B0 A2<kill>
...
B1 = B2 <- now an identify copy
...
= op B2 <- more uses
This speeds up FreeBench/neural by 29%, Olden/bh by 12%, oopack_v1p8 by 53%.
llvm-svn: 47046
This commit is contained in:
Evan Cheng
parent
87abe955fc
commit
1446726f3e
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@ -213,6 +213,20 @@ namespace llvm {
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}
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}
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/// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
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/// maps used by register allocator.
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
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if (mi2i != mi2iMap_.end()) {
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i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
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Mi2IndexMap::const_iterator it = mi2iMap_.find(MI);
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assert(it != mi2iMap_.end() && "Invalid instruction!");
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unsigned Index = it->second;
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mi2iMap_.erase(MI);
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mi2iMap_[NewMI] = Index;
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}
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}
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BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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@ -36,6 +36,8 @@
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using namespace llvm;
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STATISTIC(numJoins , "Number of interval joins performed");
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STATISTIC(numCommutes , "Number of instruction commuting performed");
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STATISTIC(numExtends , "Number of copies extended");
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STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
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STATISTIC(numAborts , "Number of times interval joining aborted");
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@ -51,6 +53,10 @@ namespace {
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cl::desc("Use new coalescer heuristic"),
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cl::init(false));
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static cl::opt<bool>
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CommuteDef("coalescer-commute-instrs",
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cl::init(false), cl::Hidden);
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RegisterPass<SimpleRegisterCoalescing>
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X("simple-register-coalescing", "Simple Register Coalescing");
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@ -104,12 +110,11 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
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assert(BValNo->def == CopyIdx &&
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"Copy doesn't define the value?");
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// AValNo is the value number in A that defines the copy, A0 in the example.
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LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
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VNInfo *AValNo = AValLR->valno;
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// If AValNo is defined as a copy from IntB, we can potentially process this.
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// AValNo is the value number in A that defines the copy, A3 in the example.
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LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
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VNInfo *AValNo = ALR->valno;
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// If AValNo is defined as a copy from IntB, we can potentially process this.
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// Get the instruction that defines this value number.
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unsigned SrcReg = AValNo->reg;
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if (!SrcReg) return false; // Not defined by a copy.
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@ -183,8 +188,199 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
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int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
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if (UIdx != -1)
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ValLREndInst->getOperand(UIdx).setIsKill(false);
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++numExtends;
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return true;
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}
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/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
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/// being the source and IntB being the dest, thus this defines a value number
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/// in IntB. If the source value number (in IntA) is defined by a commutable
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/// instruction and its other operand is coalesced to the copy dest register,
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/// see if we can transform the copy into a noop by commuting the definition. For
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/// example,
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///
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/// A3 = op A2 B0<kill>
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/// ...
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/// B1 = A3 <- this copy
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/// ...
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/// = op A3 <- more uses
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///
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/// ==>
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///
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/// B2 = op B0 A2<kill>
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/// ...
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/// B1 = B2 <- now an identify copy
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/// ...
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/// = op B2 <- more uses
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///
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/// This returns true if an interval was modified.
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///
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bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
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LiveInterval &IntB,
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MachineInstr *CopyMI) {
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if (!CommuteDef) return false;
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unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
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// BValNo is a value number in B that is defined by a copy from A. 'B3' in
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// the example above.
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LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
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VNInfo *BValNo = BLR->valno;
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++numPeep;
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// Get the location that B is defined at. Two options: either this value has
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// an unknown definition point or it is defined at CopyIdx. If unknown, we
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// can't process it.
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if (!BValNo->reg) return false;
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assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
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// AValNo is the value number in A that defines the copy, A3 in the example.
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LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
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VNInfo *AValNo = ALR->valno;
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if (AValNo->def == ~0U || AValNo->def == ~1U)
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return false;
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MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
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const TargetInstrDesc &TID = DefMI->getDesc();
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if (!TID.isCommutable())
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return false;
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int Idx = -1;
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for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = DefMI->getOperand(i);
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if (!MO.isRegister()) continue;
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unsigned Reg = MO.getReg();
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if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
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if (rep(Reg) == IntA.reg) {
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// If the dest register comes from an interval other than IntA, we
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// can't handle this.
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if (Reg != IntA.reg)
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return false;
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continue;
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}
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if (Idx != -1)
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// FIXME: Being overly careful here. We just need to figure out the
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// which register operand will become the new def.
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return false;
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Idx = i;
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}
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}
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if (Idx == -1)
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// Something like %reg1024 = add %reg1024, %reg1024
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return false;
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MachineOperand &MO = DefMI->getOperand(Idx);
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unsigned NewReg = MO.getReg();
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if (rep(NewReg) != IntB.reg || !MO.isKill())
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return false;
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// Make sure there are no other definitions of IntB that would reach the
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// uses which the new definition can reach.
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for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
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AI != AE; ++AI) {
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if (AI->valno != AValNo) continue;
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LiveInterval::Ranges::iterator BI =
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std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
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if (BI != IntB.ranges.begin())
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--BI;
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for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
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if (BI->valno == BLR->valno)
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continue;
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if (BI->start <= AI->start && BI->end > AI->start)
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return false;
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if (BI->start > AI->start && BI->start < AI->end)
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return false;
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}
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}
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// Commute def machine instr.
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MachineBasicBlock *MBB = DefMI->getParent();
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MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
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if (NewMI != DefMI) {
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li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
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MBB->insert(DefMI, NewMI);
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MBB->erase(DefMI);
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}
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unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg);
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NewMI->getOperand(OpIdx).setIsKill();
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// Update uses of IntA of the specific Val# with IntB.
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bool BHasPHIKill = BValNo->hasPHIKill;
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SmallVector<VNInfo*, 4> BDeadValNos;
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SmallVector<unsigned, 4> BKills;
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std::map<unsigned, unsigned> BExtend;
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for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
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UE = mri_->use_end(); UI != UE;) {
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MachineOperand &UseMO = UI.getOperand();
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++UI;
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MachineInstr *UseMI = UseMO.getParent();
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unsigned UseIdx = li_->getInstructionIndex(UseMI);
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LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
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if (ULR->valno != AValNo)
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continue;
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UseMO.setReg(NewReg);
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if (UseMO.isKill())
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BKills.push_back(li_->getUseIndex(UseIdx)+1);
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if (UseMI != CopyMI) {
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unsigned SrcReg, DstReg;
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if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
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continue;
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unsigned repDstReg = rep(DstReg);
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if (repDstReg != IntB.reg) {
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// Update dst register interval val# since its source register has
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// changed.
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LiveInterval &DLI = li_->getInterval(repDstReg);
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LiveInterval::iterator DLR =
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DLI.FindLiveRangeContaining(li_->getDefIndex(UseIdx));
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DLR->valno->reg = NewReg;
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ChangedCopies.insert(UseMI);
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} else {
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// This copy will become a noop. If it's defining a new val#,
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// remove that val# as well. However this live range is being
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// extended to the end of the existing live range defined by the copy.
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unsigned DefIdx = li_->getDefIndex(UseIdx);
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LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx);
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BHasPHIKill |= DLR->valno->hasPHIKill;
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assert(DLR->valno->def == DefIdx);
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BDeadValNos.push_back(DLR->valno);
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BExtend[DLR->start] = DLR->end;
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JoinedCopies.insert(UseMI);
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// If this is a kill but it's going to be removed, the last use
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// of the same val# is the new kill.
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if (UseMO.isKill()) {
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BKills.pop_back();
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}
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}
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}
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}
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// We need to insert a new liverange: [ALR.start, LastUse). It may be we can
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// simply extend BLR if CopyMI doesn't end the range.
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DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
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IntB.removeValNo(BValNo);
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for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
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IntB.removeValNo(BDeadValNos[i]);
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VNInfo *ValNo = IntB.getNextValue(ALR->start, 0, li_->getVNInfoAllocator());
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for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
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AI != AE; ++AI) {
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if (AI->valno != AValNo) continue;
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unsigned End = AI->end;
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std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
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if (EI != BExtend.end())
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End = EI->second;
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IntB.addRange(LiveRange(AI->start, End, ValNo));
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}
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IntB.addKills(ValNo, BKills);
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ValNo->hasPHIKill = BHasPHIKill;
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DOUT << " result = "; IntB.print(DOUT, tri_);
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DOUT << "\n";
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DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
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IntA.removeValNo(AValNo);
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DOUT << " result = "; IntA.print(DOUT, tri_);
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DOUT << "\n";
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++numCommutes;
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return true;
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}
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@ -217,8 +413,9 @@ bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
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LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
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if (DstLR == LI.end())
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return false;
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unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM-1;
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if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0] == KillIdx)
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unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM;
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if (DstLR->valno->kills.size() == 1 &&
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DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
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return true;
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return false;
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}
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@ -228,7 +425,7 @@ bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
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/// if the copy was successfully coalesced away. If it is not currently
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/// possible to coalesce this interval, but it may be possible if other
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/// things get coalesced, then it returns true by reference in 'Again'.
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bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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MachineInstr *CopyMI = TheCopy.MI;
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Again = false;
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@ -240,6 +437,21 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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// Get representative registers.
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unsigned SrcReg = TheCopy.SrcReg;
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unsigned DstReg = TheCopy.DstReg;
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// CopyMI has been modified due to commuting.
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if (ChangedCopies.count(CopyMI)) {
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if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg))
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;
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else if (CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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DstReg = CopyMI->getOperand(0).getReg();
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SrcReg = CopyMI->getOperand(1).getReg();
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} else
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assert(0 && "Unrecognized move instruction!");
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TheCopy.SrcReg = SrcReg;
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TheCopy.DstReg = DstReg;
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ChangedCopies.erase(CopyMI);
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}
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unsigned repSrcReg = rep(SrcReg);
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unsigned repDstReg = rep(DstReg);
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@ -280,7 +492,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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// If this is a extract_subreg where dst is a physical register, e.g.
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// cl = EXTRACT_SUBREG reg1024, 1
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// then create and update the actual physical register allocated to RHS.
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const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg);
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const TargetRegisterClass *RC = mri_->getRegClass(repSrcReg);
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for (const unsigned *SRs = tri_->getSuperRegisters(repDstReg);
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unsigned SR = *SRs; ++SRs) {
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if (repDstReg == tri_->getSubReg(SR, SubIdx) &&
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@ -439,16 +651,19 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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if (isShorten || isDead) {
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// Shorten the destination live interval.
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if (Swapped)
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SrcInt.removeRange(RemoveStart, RemoveEnd);
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SrcInt.removeRange(RemoveStart, RemoveEnd, true);
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}
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} else {
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// Coalescing failed.
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// If we can eliminate the copy without merging the live ranges, do so now.
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if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI)) {
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if (!isExtSubReg &&
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(AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
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RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
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JoinedCopies.insert(CopyMI);
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return true;
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}
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// Otherwise, we are unable to join the intervals.
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DOUT << "Interference!\n";
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@ -534,8 +749,9 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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if (vni->def && vni->def != ~1U && vni->def != ~0U) {
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MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
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unsigned SrcReg, DstReg;
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if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) &&
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JoinedCopies.count(CopyMI) == 0) {
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if (CopyMI &&
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JoinedCopies.count(CopyMI) == 0 &&
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tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
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unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
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JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
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isBackEdgeCopy(CopyMI, DstReg)));
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@ -555,7 +771,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
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// Finally, delete the copy instruction.
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JoinedCopies.insert(CopyMI);
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++numPeep;
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++numJoins;
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return true;
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}
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@ -1247,6 +1462,7 @@ bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
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return !RegClass->contains(RegB);
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}
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/// FIXME: Make use MachineRegisterInfo use information for virtual registers.
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/// lastRegisterUse - Returns the last use of the specific register between
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/// cycles Start and End. It also returns the use operand by reference. It
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/// returns NULL if there are no uses.
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@ -1361,6 +1577,7 @@ void SimpleRegisterCoalescing::releaseMemory() {
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JoinedLIs.clear();
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SubRegIdxes.clear();
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JoinedCopies.clear();
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ChangedCopies.clear();
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}
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static bool isZeroLengthInterval(LiveInterval *li) {
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@ -1373,6 +1590,7 @@ static bool isZeroLengthInterval(LiveInterval *li) {
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bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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mri_ = &fn.getRegInfo();
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tm_ = &fn.getTarget();
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tri_ = tm_->getRegisterInfo();
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tii_ = tm_->getInstrInfo();
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@ -1409,6 +1627,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
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E = JoinedCopies.end(); I != E; ++I) {
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li_->RemoveMachineInstrFromMaps(*I);
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(*I)->eraseFromParent();
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++numPeep;
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}
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// Transfer sub-registers info to MachineRegisterInfo now that coalescing
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@ -1442,7 +1661,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
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if (MO->isDead()) {
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unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
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LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
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RegInt.removeRange(MLR->start, MoveIdx+1);
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RegInt.removeRange(MLR->start, MoveIdx+1, true);
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if (RegInt.empty())
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li_->removeInterval(RegRep);
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}
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@ -80,6 +80,7 @@ namespace llvm {
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class SimpleRegisterCoalescing : public MachineFunctionPass,
|
||||
public RegisterCoalescer {
|
||||
MachineFunction* mf_;
|
||||
const MachineRegisterInfo* mri_;
|
||||
const TargetMachine* tm_;
|
||||
const TargetRegisterInfo* tri_;
|
||||
const TargetInstrInfo* tii_;
|
||||
|
|
@ -114,6 +115,9 @@ namespace llvm {
|
|||
///
|
||||
SmallPtrSet<MachineInstr*, 32> JoinedCopies;
|
||||
|
||||
/// ChangedCopies - Keep track of copies modified due to commuting.
|
||||
SmallPtrSet<MachineInstr*, 32> ChangedCopies;
|
||||
|
||||
public:
|
||||
static char ID; // Pass identifcation, replacement for typeid
|
||||
SimpleRegisterCoalescing() : MachineFunctionPass((intptr_t)&ID) {}
|
||||
|
|
@ -168,7 +172,7 @@ namespace llvm {
|
|||
/// if the copy was successfully coalesced away. If it is not currently
|
||||
/// possible to coalesce this interval, but it may be possible if other
|
||||
/// things get coalesced, then it returns true by reference in 'Again'.
|
||||
bool JoinCopy(CopyRec TheCopy, bool &Again);
|
||||
bool JoinCopy(CopyRec &TheCopy, bool &Again);
|
||||
|
||||
/// JoinIntervals - Attempt to join these two intervals. On failure, this
|
||||
/// returns false. Otherwise, if one of the intervals being joined is a
|
||||
|
|
@ -192,6 +196,9 @@ namespace llvm {
|
|||
bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
|
||||
MachineInstr *CopyMI);
|
||||
|
||||
bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
|
||||
MachineInstr *CopyMI);
|
||||
|
||||
/// AddSubRegIdxPairs - Recursively mark all the registers represented by the
|
||||
/// specified register as sub-registers. The recursion level is expected to be
|
||||
/// shallow.
|
||||
|
|
|
|||
Loading…
Reference in New Issue