forked from OSchip/llvm-project
Add more missing TB encodings to VEX instructions to allow them to be disassembled. Fixes remainder of PR10678.
llvm-svn: 138553
This commit is contained in:
Craig Topper
parent
76e3e0b554
commit
14380ff9a0
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@ -416,22 +416,22 @@ let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
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}
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defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
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"movaps", SSEPackedSingle>, VEX;
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"movaps", SSEPackedSingle>, TB, VEX;
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defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
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"movapd", SSEPackedDouble>, OpSize, VEX;
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"movapd", SSEPackedDouble>, TB, OpSize, VEX;
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defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
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"movups", SSEPackedSingle>, VEX;
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"movups", SSEPackedSingle>, TB, VEX;
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defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
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"movupd", SSEPackedDouble, 0>, OpSize, VEX;
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"movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
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defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
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"movaps", SSEPackedSingle>, VEX;
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"movaps", SSEPackedSingle>, TB, VEX;
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defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
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"movapd", SSEPackedDouble>, OpSize, VEX;
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"movapd", SSEPackedDouble>, TB, OpSize, VEX;
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defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
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"movups", SSEPackedSingle>, VEX;
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"movups", SSEPackedSingle>, TB, VEX;
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defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
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"movupd", SSEPackedDouble, 0>, OpSize, VEX;
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"movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
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defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
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"movaps", SSEPackedSingle>, TB;
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defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
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@ -1451,25 +1451,25 @@ multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
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let Defs = [EFLAGS] in {
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defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss", SSEPackedSingle>, VEX;
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"ucomiss", SSEPackedSingle>, TB, VEX;
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defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
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"ucomisd", SSEPackedDouble>, OpSize, VEX;
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"ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
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let Pattern = []<dag> in {
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defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
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"comiss", SSEPackedSingle>, VEX;
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"comiss", SSEPackedSingle>, TB, VEX;
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defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
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"comisd", SSEPackedDouble>, OpSize, VEX;
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"comisd", SSEPackedDouble>, TB, OpSize, VEX;
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}
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defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
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load, "ucomiss", SSEPackedSingle>, VEX;
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load, "ucomiss", SSEPackedSingle>, TB, VEX;
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defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
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load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
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load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
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defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
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load, "comiss", SSEPackedSingle>, VEX;
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load, "comiss", SSEPackedSingle>, TB, VEX;
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defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
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load, "comisd", SSEPackedDouble>, OpSize, VEX;
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load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
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defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss", SSEPackedSingle>, TB;
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defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
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@ -1518,19 +1518,19 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
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defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $dst|$dst, $src}",
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@ -1767,29 +1767,29 @@ multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
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let AddedComplexity = 10 in {
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defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
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VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
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VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
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VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
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VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
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VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
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VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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@ -1963,14 +1963,14 @@ let Predicates = [HasAVX] in {
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// Assembler Only
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def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
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def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
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VEX;
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def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
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def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB, OpSize,
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VEX;
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}
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@ -3184,7 +3184,7 @@ def mi : Ii8<0x70, MRMSrcMem,
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let Predicates = [HasAVX] in {
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let AddedComplexity = 5 in
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defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
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defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
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VEX;
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// SSE2 with ImmT == Imm8 and XS prefix.
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@ -3399,7 +3399,7 @@ def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
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(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
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"vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
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imm:$src2))]>, OpSize, VEX;
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imm:$src2))]>, TB, OpSize, VEX;
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def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
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(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
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"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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@ -3408,11 +3408,11 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
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// Insert
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let Predicates = [HasAVX] in {
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defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
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defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
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def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
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"vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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[]>, OpSize, VEX_4V;
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[]>, TB, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in
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