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Revert "[mips] Reordering callseq* nodes to be linear" 

This reverts commit r314507, because the original patch is causing test
failures.

llvm-svn: 316215
This commit is contained in:
Aleksandar Beserminji 2017-10-20 14:35:41 +00:00
parent 27b226fb65
commit 143572984d
8 changed files with 36 additions and 38 deletions
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39
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -2992,6 +2992,16 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (IsTailCall)
++NumTailCalls;
// Chain is the output chain of the last Load/Store or CopyToReg node.
// ByValChain is the output chain of the last Memcpy node created for copying
// byval arguments to the stack.
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = alignTo(NextStackOffset, StackAlignment);
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
SDValue StackPtr =
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
getPointerTy(DAG.getDataLayout()));
@ -3020,7 +3030,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
assert(ByValIdx < CCInfo.getInRegsParamsCount());
assert(!IsTailCall &&
"Do not tail-call optimize if there is a byval argument.");
Chain = passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
VA);
CCInfo.nextInRegsParam();
@ -3111,16 +3121,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
EVT Ty = Callee.getValueType();
bool GlobalOrExternal = false, IsCallReloc = false;
// Chain is the output chain of the last Load/Store or CopyToReg node.
// ByValChain is the output chain of the last Memcpy node created for copying
// byval arguments to the stack.
unsigned StackAlignment = TFL->getStackAlignment();
NextStackOffset = alignTo(NextStackOffset, StackAlignment);
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
if (!IsTailCall)
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
// The long-calls feature is ignored in case of PIC.
// While we do not support -mshared / -mno-shared properly,
// ignore long-calls in case of -mabicalls too.
@ -4094,7 +4094,7 @@ void MipsTargetLowering::copyByValRegs(
}
// Copy byVal arg to registers and stack.
SDValue MipsTargetLowering::passByValArg(
void MipsTargetLowering::passByValArg(
SDValue Chain, const SDLoc &DL,
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
@ -4127,7 +4127,7 @@ SDValue MipsTargetLowering::passByValArg(
// Return if the struct has been fully copied.
if (ByValSizeInBytes == OffsetInBytes)
return Chain;
return;
// Copy the remainder of the byval argument with sub-word loads and shifts.
if (LeftoverBytes) {
@ -4172,7 +4172,7 @@ SDValue MipsTargetLowering::passByValArg(
unsigned ArgReg = ArgRegs[FirstReg + I];
RegsToPass.push_back(std::make_pair(ArgReg, Val));
return Chain;
return;
}
}
@ -4182,13 +4182,12 @@ SDValue MipsTargetLowering::passByValArg(
DAG.getConstant(OffsetInBytes, DL, PtrTy));
SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
Chain = DAG.getMemcpy(
Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), Alignment,
/*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
DAG.getConstant(MemCpySize, DL, PtrTy),
Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
/*isTailCall=*/false,
MachinePointerInfo(), MachinePointerInfo());
MemOpChains.push_back(Chain);
return Chain;
}
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,

14
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -573,13 +573,13 @@ class TargetRegisterClass;
MipsCCState &State) const;
/// passByValArg - Pass a byval argument in registers or on stack.
SDValue passByValArg(SDValue Chain, const SDLoc &DL,
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
SmallVectorImpl<SDValue> &MemOpChains,
SDValue StackPtr, MachineFrameInfo &MFI,
SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
unsigned LastReg, const ISD::ArgFlagsTy &Flags,
bool isLittle, const CCValAssign &VA) const;
void passByValArg(SDValue Chain, const SDLoc &DL,
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
unsigned FirstReg, unsigned LastReg,
const ISD::ArgFlagsTy &Flags, bool isLittle,
const CCValAssign &VA) const;
/// writeVarArgRegs - Write variable function arguments passed in registers
/// to the stack. Also create a stack frame object for the first variable

11
llvm/test/CodeGen/Mips/largeimmprinting.ll
View File

@ -1,9 +1,8 @@
; RUN: llc -march=mipsel -relocation-model=pic -verify-machineinstrs < %s | \
; RUN: FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic \
; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \
; RUN: FileCheck %s -check-prefix=64
%struct.S1 = type { [65536 x i8] }

2
llvm/test/CodeGen/Mips/llvm-ir/mul.ll
View File

@ -268,7 +268,7 @@ entry:
; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7
; MM32: lw $25, %call16(__multi3)
; MM32: lw $25, %call16(__multi3)($16)
%r = mul i128 %a, %b
ret i128 %r

2
llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
View File

@ -190,7 +190,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
; 64R6: ld $25, %call16(__divti3)($gp)
; MM32: lw $25, %call16(__divti3)
; MM32: lw $25, %call16(__divti3)($16)
; MM64: ld $25, %call16(__divti3)($2)

2
llvm/test/CodeGen/Mips/llvm-ir/srem.ll
View File

@ -182,7 +182,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
; MM32: lw $25, %call16(__modti3)
; MM32: lw $25, %call16(__modti3)($16)
; MM64: ld $25, %call16(__modti3)($2)

2
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
View File

@ -152,7 +152,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
; 64-R6: ld $25, %call16(__udivti3)($gp)
; MM32: lw $25, %call16(__udivti3)
; MM32: lw $25, %call16(__udivti3)($16)
; MM64: ld $25, %call16(__udivti3)($2)

2
llvm/test/CodeGen/Mips/llvm-ir/urem.ll
View File

@ -208,7 +208,7 @@ entry:
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
; 64R6: ld $25, %call16(__umodti3)($gp)
; MM32: lw $25, %call16(__umodti3)
; MM32: lw $25, %call16(__umodti3)($16)
; MM64: ld $25, %call16(__umodti3)($2)