forked from OSchip/llvm-project
[Attributor] Only non-exact accesses require a uniform bit-pattern (=0)
If we only have exact accesses we should never require the bit-pattern to be uniform (in this case 0). Only a non-exact access should force us to require only 0 values.
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@ -378,13 +378,13 @@ static bool getPotentialCopiesOfMemoryValue(
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bool NullOnly = true;
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bool NullRequired = false;
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auto CheckForNullOnlyAndUndef = [&](Optional<Value *> V) {
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auto CheckForNullOnlyAndUndef = [&](Optional<Value *> V, bool IsExact) {
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if (!V || *V == nullptr)
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NullOnly = false;
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else if (isa<UndefValue>(*V))
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/* No op */;
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else if (isa<Constant>(*V) && cast<Constant>(*V)->isNullValue())
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NullRequired = true;
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NullRequired = !IsExact;
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else
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NullOnly = false;
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};
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@ -395,7 +395,7 @@ static bool getPotentialCopiesOfMemoryValue(
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LLVM_DEBUG(dbgs() << "Failed to get initial value: " << *Obj << "\n");
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return false;
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}
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CheckForNullOnlyAndUndef(InitialValue);
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CheckForNullOnlyAndUndef(InitialValue, /* IsExact */ true);
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NewCopies.push_back(InitialValue);
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NewCopyOrigins.push_back(nullptr);
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}
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@ -405,7 +405,7 @@ static bool getPotentialCopiesOfMemoryValue(
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return true;
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if (IsLoad && Acc.isWrittenValueYetUndetermined())
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return true;
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CheckForNullOnlyAndUndef(Acc.getContent());
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CheckForNullOnlyAndUndef(Acc.getContent(), IsExact);
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if (OnlyExact && !IsExact && !NullOnly &&
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!isa_and_nonnull<UndefValue>(Acc.getWrittenValue())) {
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LLVM_DEBUG(dbgs() << "Non exact access " << *Acc.getRemoteInst()
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@ -288,7 +288,7 @@ define internal void @level2a(i32* %addr) {
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; IS__TUNIT____-NEXT: entry:
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; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @ReachableNonKernel to i32*), align 4
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; IS__TUNIT____-NEXT: [[TMP1:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @UnreachableNonKernel to i32*), align 4
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; IS__TUNIT____-NEXT: call void @use(i32 [[TMP0]], i32 [[TMP1]], i32 17) #[[ATTR6]]
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; IS__TUNIT____-NEXT: call void @use(i32 noundef [[TMP0]], i32 noundef [[TMP1]], i32 17) #[[ATTR6]]
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; IS__TUNIT____-NEXT: ret void
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;
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; IS__CGSCC____: Function Attrs: nosync nounwind
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@ -298,7 +298,7 @@ define internal void @level2a(i32* %addr) {
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; IS__CGSCC____-NEXT: [[TMP0:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @ReachableNonKernel to i32*), align 4
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; IS__CGSCC____-NEXT: [[TMP1:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @UnreachableNonKernel to i32*), align 4
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; IS__CGSCC____-NEXT: [[QQQQ2:%.*]] = load i32, i32* [[ADDR]], align 4
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; IS__CGSCC____-NEXT: call void @use(i32 [[TMP0]], i32 [[TMP1]], i32 [[QQQQ2]]) #[[ATTR4]]
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; IS__CGSCC____-NEXT: call void @use(i32 noundef [[TMP0]], i32 noundef [[TMP1]], i32 [[QQQQ2]]) #[[ATTR4]]
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; IS__CGSCC____-NEXT: ret void
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;
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entry:
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@ -316,7 +316,7 @@ define internal void @level2b(i32* %addr) {
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; IS__TUNIT____-NEXT: entry:
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; IS__TUNIT____-NEXT: [[TMP0:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @ReachableNonKernel to i32*), align 4
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; IS__TUNIT____-NEXT: [[TMP1:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @UnreachableNonKernel to i32*), align 4
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; IS__TUNIT____-NEXT: call void @use(i32 [[TMP0]], i32 [[TMP1]], i32 17) #[[ATTR6]]
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; IS__TUNIT____-NEXT: call void @use(i32 noundef [[TMP0]], i32 noundef [[TMP1]], i32 17) #[[ATTR6]]
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; IS__TUNIT____-NEXT: ret void
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;
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; IS__CGSCC____: Function Attrs: nosync nounwind
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@ -326,7 +326,7 @@ define internal void @level2b(i32* %addr) {
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; IS__CGSCC____-NEXT: [[TMP0:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @ReachableNonKernel to i32*), align 4
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; IS__CGSCC____-NEXT: [[TMP1:%.*]] = load i32, i32* addrspacecast (i32 addrspace(3)* @UnreachableNonKernel to i32*), align 4
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; IS__CGSCC____-NEXT: [[TMP2:%.*]] = load i32, i32* [[ADDR]], align 4
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; IS__CGSCC____-NEXT: call void @use(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) #[[ATTR4]]
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; IS__CGSCC____-NEXT: call void @use(i32 noundef [[TMP0]], i32 noundef [[TMP1]], i32 [[TMP2]]) #[[ATTR4]]
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; IS__CGSCC____-NEXT: ret void
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;
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entry:
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