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AMDGPU/GlobalISel: Use a more correct getValueMapping 

This was finding the wrong size registers for anything with
more than 2 components.

Patch by Tom Stellard

llvm-svn: 326483
This commit is contained in:
Matt Arsenault 2018-03-01 21:08:51 +00:00
parent 62669ede94
commit 1422a19a88
1 changed files with 56 additions and 19 deletions
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75
llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def
View File

@ -16,51 +16,88 @@ namespace AMDGPU {
enum PartialMappingIdx {
None = - 1,
PM_SGPR32 = 0,
PM_SGPR64 = 1,
PM_VGPR32 = 2,
PM_VGPR64 = 3,
PM_SGPR1 = 4,
PM_VGPR1 = 5,
PM_SGPR1 = 0,
PM_SGPR16 = 4,
PM_SGPR32 = 5,
PM_SGPR64 = 6,
PM_SGPR128 = 7,
PM_SGPR256 = 8,
PM_SGPR512 = 9,
PM_VGPR1 = 10,
PM_VGPR16 = 14,
PM_VGPR32 = 15,
PM_VGPR64 = 16,
PM_VGPR128 = 17,
PM_VGPR256 = 18,
PM_VGPR512 = 19,
PM_SGPR96 = 20,
PM_VGPR96 = 21
};
const RegisterBankInfo::PartialMapping PartMappings[] {
// StartIdx, Length, RegBank
{0, 1, SCCRegBank},
{0, 16, SGPRRegBank},
{0, 32, SGPRRegBank},
{0, 64, SGPRRegBank},
{0, 128, SGPRRegBank},
{0, 256, SGPRRegBank},
{0, 512, SGPRRegBank},
{0, 1, SGPRRegBank},
{0, 16, VGPRRegBank},
{0, 32, VGPRRegBank},
{0, 64, VGPRRegBank},
{0, 1, SCCRegBank},
{0, 1, SGPRRegBank}
{0, 128, VGPRRegBank},
{0, 256, VGPRRegBank},
{0, 512, VGPRRegBank},
{0, 96, SGPRRegBank},
{0, 96, VGPRRegBank},
};
const RegisterBankInfo::ValueMapping ValMappings[] {
// SGPR 32-bit
{&PartMappings[0], 1},
// SGPR 64-bit
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
{&PartMappings[1], 1},
// VGPR 32-bit
{&PartMappings[2], 1},
// VGPR 64-bit
{&PartMappings[3], 1},
{&PartMappings[4], 1},
{&PartMappings[5], 1}
{&PartMappings[5], 1},
{&PartMappings[6], 1},
{&PartMappings[7], 1},
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
{&PartMappings[8], 1},
{&PartMappings[9], 1},
{&PartMappings[10], 1},
{&PartMappings[11], 1},
{&PartMappings[12], 1},
{&PartMappings[13], 1},
{&PartMappings[14], 1},
{&PartMappings[15], 1}
};
enum ValueMappingIdx {
SGPRStartIdx = 0,
VGPRStartIdx = 2
VGPRStartIdx = 10
};
const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
unsigned Size) {
unsigned Idx;
if (Size == 1) {
switch (Size) {
case 1:
Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
} else {
assert(Size % 32 == 0);
Idx = BankID == AMDGPU::SGPRRegBankID ? SGPRStartIdx : VGPRStartIdx;
Idx += (Size / 32) - 1;
break;
case 96:
Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
break;
default:
Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
Idx += llvm::countTrailingZeros(Size);
break;
}
return &ValMappings[Idx];
}