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More A9 itineraries 

llvm-svn: 100655
This commit is contained in:
Anton Korobeynikov 2010-04-07 18:20:29 +00:00
parent 1a1af5a830
commit 140a65ce0b
2 changed files with 30 additions and 2 deletions
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4
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -2513,8 +2513,8 @@ def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD, def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
"vpadd", "i32", "vpadd", "i32",
v2i32, v2i32, int_arm_neon_vpadd, 0>; v2i32, v2i32, int_arm_neon_vpadd, 0>;
def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm, IIC_VSHLD, def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
"vpadd", "f32", IIC_VBIND, "vpadd", "f32",
v2f32, v2f32, int_arm_neon_vpadd, 0>; v2f32, v2f32, int_arm_neon_vpadd, 0>;
// VPADDL : Vector Pairwise Add Long // VPADDL : Vector Pairwise Add Long

28
llvm/lib/Target/ARM/ARMScheduleV7.td
View File

@ -793,6 +793,34 @@ def CortexA9Itineraries : ProcessorItineraries<[
// NEON // NEON
// Issue through integer pipeline, and execute in NEON unit. // Issue through integer pipeline, and execute in NEON unit.
//
// Double-register Integer Unary
InstrItinData<IIC_VUNAiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 2]>,
//
// Quad-register Integer Unary
InstrItinData<IIC_VUNAiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 2]>,
//
// Double-register Integer Q-Unary
InstrItinData<IIC_VQUNAiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 1]>,
//
// Quad-register Integer CountQ-Unary
InstrItinData<IIC_VQUNAiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
// Extra 3 latency cycle since wbck is 6 cycles
InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
InstrStage<1, [FU_NPipe]>], [4, 1]>,
// //
// Double-register Integer Binary // Double-register Integer Binary
InstrItinData<IIC_VBINiD, [InstrStage2<1, [FU_DRegsN], 0, Required>, InstrItinData<IIC_VBINiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,