forked from OSchip/llvm-project
[X86][AVX512] Tag VPERMILV instruction scheduler class
llvm-svn: 319316
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2b6338b2bc
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1401a75341
llvm/lib/Target/X86
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@ -5595,21 +5595,23 @@ defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
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// AVX-512 - VPERMIL
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// AVX-512 - VPERMIL
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
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multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
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OpndItins itins, X86VectorVTInfo _,
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X86VectorVTInfo Ctrl> {
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defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
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defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
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(ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1,
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(_.VT (OpNode _.RC:$src1,
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(Ctrl.VT Ctrl.RC:$src2)))>,
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(Ctrl.VT Ctrl.RC:$src2))), itins.rr>,
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T8PD, EVEX_4V;
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T8PD, EVEX_4V, Sched<[itins.Sched]>;
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defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
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defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
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(ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode
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(_.VT (OpNode
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_.RC:$src1,
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_.RC:$src1,
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(Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
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(Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2))))),
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T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
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itins.rm>, T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
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defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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"${src2}"##_.BroadcastStr##", $src1",
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"${src2}"##_.BroadcastStr##", $src1",
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@ -5617,28 +5619,29 @@ multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
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(_.VT (OpNode
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(_.VT (OpNode
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_.RC:$src1,
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_.RC:$src1,
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(Ctrl.VT (X86VBroadcast
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(Ctrl.VT (X86VBroadcast
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(Ctrl.ScalarLdFrag addr:$src2)))))>,
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(Ctrl.ScalarLdFrag addr:$src2))))),
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T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
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itins.rm>, T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
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multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
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AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
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OpndItins itins, AVX512VLVectorVTInfo _,
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AVX512VLVectorVTInfo Ctrl> {
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let Predicates = [HasAVX512] in {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
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defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, itins,
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Ctrl.info512>, EVEX_V512;
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_.info512, Ctrl.info512>, EVEX_V512;
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}
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}
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let Predicates = [HasAVX512, HasVLX] in {
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let Predicates = [HasAVX512, HasVLX] in {
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defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
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defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, itins,
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Ctrl.info128>, EVEX_V128;
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_.info128, Ctrl.info128>, EVEX_V128;
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defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
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defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, itins,
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Ctrl.info256>, EVEX_V256;
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_.info256, Ctrl.info256>, EVEX_V256;
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}
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}
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}
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}
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multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
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multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
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AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
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AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
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defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, AVX_VPERMILV, _, Ctrl>;
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defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
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defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
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defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
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X86VPermilpi, _>,
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X86VPermilpi, _>,
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EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
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EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
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@ -5650,6 +5653,7 @@ defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
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let ExeDomain = SSEPackedDouble in
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let ExeDomain = SSEPackedDouble in
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defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
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defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
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avx512vl_i64_info>, VEX_W;
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avx512vl_i64_info>, VEX_W;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
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// AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -7612,6 +7612,17 @@ defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// VPERMIL - Permute Single and Double Floating-Point Values
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// VPERMIL - Permute Single and Double Floating-Point Values
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//
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//
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let Sched = WriteFShuffle in
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def AVX_VPERMILV : OpndItins<
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IIC_SSE_SHUFP, IIC_SSE_SHUFP
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>;
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let Sched = WriteFShuffle in
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def AVX_VPERMIL : OpndItins<
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IIC_SSE_SHUFP, IIC_SSE_SHUFP
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>;
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multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
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multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop_f,
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RegisterClass RC, X86MemOperand x86memop_f,
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X86MemOperand x86memop_i, PatFrag i_frag,
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X86MemOperand x86memop_i, PatFrag i_frag,
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