forked from OSchip/llvm-project
[Sparc] LLONG is not lock-free atomic on v8
Differential Revision: https://reviews.llvm.org/D26286 llvm-svn: 286376
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@ -6803,7 +6803,10 @@ public:
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PtrDiffType = SignedLong;
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break;
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}
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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// Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
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// on up to 64 bits.
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MaxAtomicPromoteWidth = 64;
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MaxAtomicInlineWidth = 32;
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}
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void getTargetDefines(const LangOptions &Opts,
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@ -3,7 +3,8 @@
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// RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC64
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// RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
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// RUN: %clang_cc1 -triple mips64el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
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// RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARC
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// RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV8 -check-prefix=SPARC
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// RUN: %clang_cc1 -triple sparcv9-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV9 -check-prefix=SPARC
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unsigned char c1, c2;
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unsigned short s1, s2;
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@ -99,8 +100,10 @@ void test1(void) {
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// SPARC: store atomic i16 {{.*}}, i16* @s1 seq_cst
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// SPARC: = load atomic i32, i32* @i1 seq_cst
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// SPARC: store atomic i32 {{.*}}, i32* @i1 seq_cst
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// SPARC: = load atomic i64, i64* @ll1 seq_cst
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// SPARC: store atomic i64 {{.*}}, i64* @ll1 seq_cst
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// SPARC: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0)
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// SPARC: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0)
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// SPARCV8: call i64 @__atomic_load_8(i8* bitcast (i64* @ll1 to i8*)
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// SPARCV8: call void @__atomic_store_8(i8* bitcast (i64* @ll1 to i8*), i64
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// SPARCV9: load atomic i64, i64* @ll1 seq_cst, align 8
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// SPARCV9: store atomic i64 %7, i64* @ll1 seq_cst, align 8
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// SPARCV8: call void @__atomic_load(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0)
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// SPARCV8: call void @__atomic_store(i32 100, i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a1, i32 0, i32 0), i8* getelementptr inbounds ([100 x i8], [100 x i8]* @a2, i32 0, i32 0)
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}
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@ -6913,6 +6913,7 @@
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// SPARC:#define __FLT_MIN_EXP__ (-125)
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// SPARC:#define __FLT_MIN__ 1.17549435e-38F
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// SPARC:#define __FLT_RADIX__ 2
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// SPARC:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
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// SPARC:#define __INT16_C_SUFFIX__
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// SPARC:#define __INT16_FMTd__ "hd"
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// SPARC:#define __INT16_FMTi__ "hi"
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