forked from OSchip/llvm-project
Change ARM asm strings to separate opcode from operands with a tab instead of a space.
llvm-svn: 85178
This commit is contained in:
Evan Cheng
parent
a70c6dff97
commit
13edef55b6
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@ -370,19 +370,19 @@ include "ARMInstrFormats.td"
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multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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IIC_iALUi, opc, " $dst, $a, $b",
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IIC_iALUi, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
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let Inst{25} = 1;
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}
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
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IIC_iALUr, opc, " $dst, $a, $b",
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IIC_iALUr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
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let Inst{4} = 0;
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let Inst{25} = 0;
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let isCommutable = Commutable;
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}
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, opc, " $dst, $a, $b",
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IIC_iALUsr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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@ -396,13 +396,13 @@ let Defs = [CPSR] in {
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multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
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IIC_iALUi, opc, "s $dst, $a, $b",
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IIC_iALUi, opc, "s\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
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let Inst{20} = 1;
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let Inst{25} = 1;
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}
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def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
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IIC_iALUr, opc, "s $dst, $a, $b",
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IIC_iALUr, opc, "s\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
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let isCommutable = Commutable;
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let Inst{4} = 0;
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@ -410,7 +410,7 @@ multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Inst{25} = 0;
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}
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def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
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IIC_iALUsr, opc, "s $dst, $a, $b",
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IIC_iALUsr, opc, "s\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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@ -427,13 +427,13 @@ let Defs = [CPSR] in {
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multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
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opc, " $a, $b",
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opc, "\t$a, $b",
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[(opnode GPR:$a, so_imm:$b)]> {
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let Inst{20} = 1;
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let Inst{25} = 1;
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}
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def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
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opc, " $a, $b",
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opc, "\t$a, $b",
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[(opnode GPR:$a, GPR:$b)]> {
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let Inst{4} = 0;
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let Inst{20} = 1;
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@ -441,7 +441,7 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
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let isCommutable = Commutable;
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}
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def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
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opc, " $a, $b",
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opc, "\t$a, $b",
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[(opnode GPR:$a, so_reg:$b)]> {
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let Inst{4} = 1;
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let Inst{7} = 0;
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@ -456,13 +456,13 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
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/// FIXME: Remove the 'r' variant. Its rot_imm is zero.
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multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
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IIC_iUNAr, opc, " $dst, $src",
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IIC_iUNAr, opc, "\t$dst, $src",
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[(set GPR:$dst, (opnode GPR:$src))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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}
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def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
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IIC_iUNAsi, opc, " $dst, $src, ror $rot",
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IIC_iUNAsi, opc, "\t$dst, $src, ror $rot",
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[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]> {
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let Inst{19-16} = 0b1111;
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@ -473,11 +473,11 @@ multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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/// register and one whose operand is a register rotated by 8/16/24.
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multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
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def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
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IIC_iALUr, opc, " $dst, $LHS, $RHS",
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IIC_iALUr, opc, "\t$dst, $LHS, $RHS",
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[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
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Requires<[IsARM, HasV6]>;
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def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
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IIC_iALUsi, opc, " $dst, $LHS, $RHS, ror $rot",
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IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot",
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[(set GPR:$dst, (opnode GPR:$LHS,
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(rotr GPR:$RHS, rot_imm:$rot)))]>,
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Requires<[IsARM, HasV6]>;
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@ -488,13 +488,13 @@ let Uses = [CPSR] in {
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multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, IIC_iALUi, opc, " $dst, $a, $b",
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DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let Inst{25} = 1;
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}
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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DPFrm, IIC_iALUr, opc, " $dst, $a, $b",
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DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let isCommutable = Commutable;
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@ -502,7 +502,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Inst{25} = 0;
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}
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, IIC_iALUsr, opc, " $dst, $a, $b",
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DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUnused]> {
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let Inst{4} = 1;
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@ -511,7 +511,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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// Carry setting variants
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def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
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DPFrm, IIC_iALUi, !strconcat(opc, "s $dst, $a, $b"),
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DPFrm, IIC_iALUi, !strconcat(opc, "s\t$dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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@ -519,7 +519,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Inst{25} = 1;
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}
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def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
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DPFrm, IIC_iALUr, !strconcat(opc, "s $dst, $a, $b"),
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DPFrm, IIC_iALUr, !strconcat(opc, "s\t$dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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@ -528,7 +528,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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let Inst{25} = 0;
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}
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def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
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DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s $dst, $a, $b"),
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DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s\t$dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
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Requires<[IsARM, CarryDefIsUsed]> {
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let Defs = [CPSR];
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@ -579,42 +579,42 @@ PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
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// Address computation and loads and stores in PIC mode.
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let isNotDuplicable = 1 in {
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def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
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Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p $dst, pc, $a",
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Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a",
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[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
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let AddedComplexity = 10 in {
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let canFoldAsLoad = 1 in
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def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p $dst, $addr",
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
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[(set GPR:$dst, (load addrmodepc:$addr))]>;
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def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h $dst, $addr",
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h\t$dst, $addr",
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[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
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def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b $dst, $addr",
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b\t$dst, $addr",
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[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
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def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh $dst, $addr",
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh\t$dst, $addr",
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[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
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def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb $dst, $addr",
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Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb\t$dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
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}
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let AddedComplexity = 10 in {
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def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p $src, $addr",
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr",
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[(store GPR:$src, addrmodepc:$addr)]>;
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def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h $src, $addr",
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h\t$src, $addr",
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[(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
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def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b $src, $addr",
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Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b\t$src, $addr",
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[(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
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}
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} // isNotDuplicable = 1
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@ -624,10 +624,10 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
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// assembler.
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def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
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Pseudo, IIC_iALUi,
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!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
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"${:private}PCRELL${:uid}+8))\n"),
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!strconcat("${:private}PCRELL${:uid}:\n\t",
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"add$p $dst, pc, #${:private}PCRELV${:uid}")),
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!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
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"${:private}PCRELL${:uid}+8))\n"),
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!strconcat("${:private}PCRELL${:uid}:\n\t",
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"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
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[]>;
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def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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@ -637,7 +637,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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"(${label}_${id}-(",
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"${:private}PCRELL${:uid}+8))\n"),
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!strconcat("${:private}PCRELL${:uid}:\n\t",
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"add$p $dst, pc, #${:private}PCRELV${:uid}")),
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"add$p\t$dst, pc, #${:private}PCRELV${:uid}")),
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[]> {
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let Inst{25} = 1;
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}
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@ -648,7 +648,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in
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def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
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"bx", " lr", [(ARMretflag)]> {
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"bx", "\tlr", [(ARMretflag)]> {
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let Inst{7-4} = 0b0001;
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let Inst{19-8} = 0b111111111111;
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let Inst{27-20} = 0b00010010;
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@ -660,7 +660,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def LDM_RET : AXI4ld<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
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LdStMulFrm, IIC_Br, "ldm${p}${addr:submode}\t$addr, $wb",
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[]>;
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// On non-Darwin platforms R9 is callee-saved.
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@ -670,18 +670,18 @@ let isCall = 1,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
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def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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IIC_Br, "bl ${func:call}",
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IIC_Br, "bl\t${func:call}",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsARM, IsNotDarwin]>;
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def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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IIC_Br, "bl", " ${func:call}",
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IIC_Br, "bl", "\t${func:call}",
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[(ARMcall_pred tglobaladdr:$func)]>,
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Requires<[IsARM, IsNotDarwin]>;
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// ARMv5T and above
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def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
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IIC_Br, "blx $func",
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IIC_Br, "blx\t$func",
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[(ARMcall GPR:$func)]>,
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Requires<[IsARM, HasV5T, IsNotDarwin]> {
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let Inst{7-4} = 0b0011;
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@ -691,7 +691,7 @@ let isCall = 1,
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// ARMv4T
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def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
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IIC_Br, "mov lr, pc\n\tbx $func",
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IIC_Br, "mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink GPR:$func)]>,
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Requires<[IsARM, IsNotDarwin]> {
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let Inst{7-4} = 0b0001;
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@ -707,17 +707,17 @@ let isCall = 1,
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D16, D17, D18, D19, D20, D21, D22, D23,
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D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
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def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
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IIC_Br, "bl ${func:call}",
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IIC_Br, "bl\t${func:call}",
|
||||
[(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
|
||||
|
||||
def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
|
||||
IIC_Br, "bl", " ${func:call}",
|
||||
IIC_Br, "bl", "\t${func:call}",
|
||||
[(ARMcall_pred tglobaladdr:$func)]>,
|
||||
Requires<[IsARM, IsDarwin]>;
|
||||
|
||||
// ARMv5T and above
|
||||
def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
|
||||
IIC_Br, "blx $func",
|
||||
IIC_Br, "blx\t$func",
|
||||
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
|
||||
let Inst{7-4} = 0b0011;
|
||||
let Inst{19-8} = 0b111111111111;
|
||||
|
|
@ -726,7 +726,7 @@ let isCall = 1,
|
|||
|
||||
// ARMv4T
|
||||
def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
|
||||
IIC_Br, "mov lr, pc\n\tbx $func",
|
||||
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
|
||||
[(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
|
||||
let Inst{7-4} = 0b0001;
|
||||
let Inst{19-8} = 0b111111111111;
|
||||
|
|
@ -739,11 +739,11 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
let isBarrier = 1 in {
|
||||
let isPredicable = 1 in
|
||||
def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
|
||||
"b $target", [(br bb:$target)]>;
|
||||
"b\t$target", [(br bb:$target)]>;
|
||||
|
||||
let isNotDuplicable = 1, isIndirectBranch = 1 in {
|
||||
def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
|
||||
IIC_Br, "mov pc, $target \n$jt",
|
||||
IIC_Br, "mov\tpc, $target \n$jt",
|
||||
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
|
||||
let Inst{20} = 0; // S Bit
|
||||
let Inst{24-21} = 0b1101;
|
||||
|
|
@ -751,7 +751,7 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
}
|
||||
def BR_JTm : JTI<(outs),
|
||||
(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
|
||||
IIC_Br, "ldr pc, $target \n$jt",
|
||||
IIC_Br, "ldr\tpc, $target \n$jt",
|
||||
[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
|
||||
imm:$id)]> {
|
||||
let Inst{20} = 1; // L bit
|
||||
|
|
@ -762,7 +762,7 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
}
|
||||
def BR_JTadd : JTI<(outs),
|
||||
(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
|
||||
IIC_Br, "add pc, $target, $idx \n$jt",
|
||||
IIC_Br, "add\tpc, $target, $idx \n$jt",
|
||||
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
|
||||
imm:$id)]> {
|
||||
let Inst{20} = 0; // S bit
|
||||
|
|
@ -775,7 +775,7 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
|
||||
// a two-value operand where a dag node expects two operands. :(
|
||||
def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
|
||||
IIC_Br, "b", " $target",
|
||||
IIC_Br, "b", "\t$target",
|
||||
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
|
||||
}
|
||||
|
||||
|
|
@ -786,140 +786,140 @@ let isBranch = 1, isTerminator = 1 in {
|
|||
// Load
|
||||
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
||||
def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
|
||||
"ldr", " $dst, $addr",
|
||||
"ldr", "\t$dst, $addr",
|
||||
[(set GPR:$dst, (load addrmode2:$addr))]>;
|
||||
|
||||
// Special LDR for loads from non-pc-relative constpools.
|
||||
let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
|
||||
def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
|
||||
"ldr", " $dst, $addr", []>;
|
||||
"ldr", "\t$dst, $addr", []>;
|
||||
|
||||
// Loads with zero extension
|
||||
def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
||||
IIC_iLoadr, "ldr", "h $dst, $addr",
|
||||
IIC_iLoadr, "ldr", "h\t$dst, $addr",
|
||||
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
|
||||
|
||||
def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
|
||||
IIC_iLoadr, "ldr", "b $dst, $addr",
|
||||
IIC_iLoadr, "ldr", "b\t$dst, $addr",
|
||||
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
|
||||
|
||||
// Loads with sign extension
|
||||
def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
||||
IIC_iLoadr, "ldr", "sh $dst, $addr",
|
||||
IIC_iLoadr, "ldr", "sh\t$dst, $addr",
|
||||
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
|
||||
|
||||
def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
|
||||
IIC_iLoadr, "ldr", "sb $dst, $addr",
|
||||
IIC_iLoadr, "ldr", "sb\t$dst, $addr",
|
||||
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
|
||||
|
||||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
|
||||
// Load doubleword
|
||||
def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
|
||||
IIC_iLoadr, "ldr", "d $dst1, $addr",
|
||||
IIC_iLoadr, "ldr", "d\t$dst1, $addr",
|
||||
[]>, Requires<[IsARM, HasV5TE]>;
|
||||
|
||||
// Indexed loads
|
||||
def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode2:$addr), LdFrm, IIC_iLoadru,
|
||||
"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
"ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
|
||||
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
"ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
"ldr", "h\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
"ldr", "h\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode2:$addr), LdFrm, IIC_iLoadru,
|
||||
"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
"ldr", "b\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
|
||||
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
"ldr", "b\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
"ldr", "sh\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
"ldr", "sh\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
|
||||
def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
"ldr", "sb\t$dst, $addr!", "$addr.base = $base_wb", []>;
|
||||
|
||||
def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
|
||||
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
|
||||
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
"ldr", "sb\t$dst, [$base], $offset", "$base = $base_wb", []>;
|
||||
}
|
||||
|
||||
// Store
|
||||
def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
|
||||
"str", " $src, $addr",
|
||||
"str", "\t$src, $addr",
|
||||
[(store GPR:$src, addrmode2:$addr)]>;
|
||||
|
||||
// Stores with truncate
|
||||
def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
|
||||
"str", "h $src, $addr",
|
||||
"str", "h\t$src, $addr",
|
||||
[(truncstorei16 GPR:$src, addrmode3:$addr)]>;
|
||||
|
||||
def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
|
||||
"str", "b $src, $addr",
|
||||
"str", "b\t$src, $addr",
|
||||
[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
|
||||
|
||||
// Store doubleword
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
|
||||
StMiscFrm, IIC_iStorer,
|
||||
"str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
|
||||
"str", "d\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
|
||||
|
||||
// Indexed stores
|
||||
def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base, am2offset:$offset),
|
||||
StFrm, IIC_iStoreru,
|
||||
"str", " $src, [$base, $offset]!", "$base = $base_wb",
|
||||
"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
||||
|
||||
def STR_POST : AI2stwpo<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
||||
StFrm, IIC_iStoreru,
|
||||
"str", " $src, [$base], $offset", "$base = $base_wb",
|
||||
"str", "\t$src, [$base], $offset", "$base = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
|
||||
|
||||
def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am3offset:$offset),
|
||||
StMiscFrm, IIC_iStoreru,
|
||||
"str", "h $src, [$base, $offset]!", "$base = $base_wb",
|
||||
"str", "h\t$src, [$base, $offset]!", "$base = $base_wb",
|
||||
[(set GPR:$base_wb,
|
||||
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
|
||||
|
||||
def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am3offset:$offset),
|
||||
StMiscFrm, IIC_iStoreru,
|
||||
"str", "h $src, [$base], $offset", "$base = $base_wb",
|
||||
"str", "h\t$src, [$base], $offset", "$base = $base_wb",
|
||||
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
|
||||
GPR:$base, am3offset:$offset))]>;
|
||||
|
||||
def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
||||
StFrm, IIC_iStoreru,
|
||||
"str", "b $src, [$base, $offset]!", "$base = $base_wb",
|
||||
"str", "b\t$src, [$base, $offset]!", "$base = $base_wb",
|
||||
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
|
||||
GPR:$base, am2offset:$offset))]>;
|
||||
|
||||
def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
|
||||
(ins GPR:$src, GPR:$base,am2offset:$offset),
|
||||
StFrm, IIC_iStoreru,
|
||||
"str", "b $src, [$base], $offset", "$base = $base_wb",
|
||||
"str", "b\t$src, [$base], $offset", "$base = $base_wb",
|
||||
[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
|
||||
GPR:$base, am2offset:$offset))]>;
|
||||
|
||||
|
|
@ -930,13 +930,13 @@ def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
|
|||
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
|
||||
def LDM : AXI4ld<(outs),
|
||||
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
|
||||
LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
|
||||
LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode}\t$addr, $wb",
|
||||
[]>;
|
||||
|
||||
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
|
||||
def STM : AXI4st<(outs),
|
||||
(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
|
||||
LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
|
||||
LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode}\t$addr, $wb",
|
||||
[]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -945,14 +945,14 @@ def STM : AXI4st<(outs),
|
|||
|
||||
let neverHasSideEffects = 1 in
|
||||
def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
|
||||
"mov", " $dst, $src", []>, UnaryDP {
|
||||
"mov", "\t$dst, $src", []>, UnaryDP {
|
||||
let Inst{4} = 0;
|
||||
let Inst{25} = 0;
|
||||
}
|
||||
|
||||
def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
|
||||
DPSoRegFrm, IIC_iMOVsr,
|
||||
"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
|
||||
"mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP {
|
||||
let Inst{4} = 1;
|
||||
let Inst{7} = 0;
|
||||
let Inst{25} = 0;
|
||||
|
|
@ -960,14 +960,14 @@ def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
|
|||
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
||||
def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
|
||||
"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
|
||||
"mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
||||
def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
|
||||
DPFrm, IIC_iMOVi,
|
||||
"movw", " $dst, $src",
|
||||
"movw", "\t$dst, $src",
|
||||
[(set GPR:$dst, imm0_65535:$src)]>,
|
||||
Requires<[IsARM, HasV6T2]> {
|
||||
let Inst{20} = 0;
|
||||
|
|
@ -977,7 +977,7 @@ def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
|
|||
let Constraints = "$src = $dst" in
|
||||
def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
|
||||
DPFrm, IIC_iMOVi,
|
||||
"movt", " $dst, $imm",
|
||||
"movt", "\t$dst, $imm",
|
||||
[(set GPR:$dst,
|
||||
(or (and GPR:$src, 0xffff),
|
||||
lo16AllZero:$imm))]>, UnaryDP,
|
||||
|
|
@ -991,7 +991,7 @@ def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
|
|||
|
||||
let Uses = [CPSR] in
|
||||
def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
|
||||
"mov", " $dst, $src, rrx",
|
||||
"mov", "\t$dst, $src, rrx",
|
||||
[(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
|
||||
|
||||
// These aren't really mov instructions, but we have to define them this way
|
||||
|
|
@ -999,10 +999,10 @@ def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
|
|||
|
||||
let Defs = [CPSR] in {
|
||||
def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
|
||||
IIC_iMOVsi, "mov", "s $dst, $src, lsr #1",
|
||||
IIC_iMOVsi, "mov", "s\t$dst, $src, lsr #1",
|
||||
[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
|
||||
def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
|
||||
IIC_iMOVsi, "mov", "s $dst, $src, asr #1",
|
||||
IIC_iMOVsi, "mov", "s\t$dst, $src, asr #1",
|
||||
[(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
|
||||
}
|
||||
|
||||
|
|
@ -1053,7 +1053,7 @@ defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
|
|||
def SBFX : I<(outs GPR:$dst),
|
||||
(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
|
||||
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
|
||||
"sbfx", " $dst, $src, $lsb, $width", "", []>,
|
||||
"sbfx", "\t$dst, $src, $lsb, $width", "", []>,
|
||||
Requires<[IsARM, HasV6T2]> {
|
||||
let Inst{27-21} = 0b0111101;
|
||||
let Inst{6-4} = 0b101;
|
||||
|
|
@ -1062,7 +1062,7 @@ def SBFX : I<(outs GPR:$dst),
|
|||
def UBFX : I<(outs GPR:$dst),
|
||||
(ins GPR:$src, imm0_31:$lsb, imm0_31:$width),
|
||||
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
|
||||
"ubfx", " $dst, $src, $lsb, $width", "", []>,
|
||||
"ubfx", "\t$dst, $src, $lsb, $width", "", []>,
|
||||
Requires<[IsARM, HasV6T2]> {
|
||||
let Inst{27-21} = 0b0111111;
|
||||
let Inst{6-4} = 0b101;
|
||||
|
|
@ -1090,14 +1090,14 @@ defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
|
|||
|
||||
// These don't define reg/reg forms, because they are handled above.
|
||||
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
||||
IIC_iALUi, "rsb", " $dst, $a, $b",
|
||||
IIC_iALUi, "rsb", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
|
||||
let Inst{20} = 0;
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
|
||||
def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
||||
IIC_iALUsr, "rsb", " $dst, $a, $b",
|
||||
IIC_iALUsr, "rsb", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{7} = 0;
|
||||
|
|
@ -1108,13 +1108,13 @@ def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|||
// RSB with 's' bit set.
|
||||
let Defs = [CPSR] in {
|
||||
def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
|
||||
IIC_iALUi, "rsb", "s $dst, $a, $b",
|
||||
IIC_iALUi, "rsb", "s\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
|
||||
let Inst{20} = 1;
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
||||
IIC_iALUsr, "rsb", "s $dst, $a, $b",
|
||||
IIC_iALUsr, "rsb", "s\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> {
|
||||
let Inst{4} = 1;
|
||||
let Inst{7} = 0;
|
||||
|
|
@ -1125,14 +1125,14 @@ def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
|
|||
|
||||
let Uses = [CPSR] in {
|
||||
def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
||||
DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
|
||||
DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
|
||||
Requires<[IsARM, CarryDefIsUnused]> {
|
||||
let Inst{20} = 0;
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
||||
DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
|
||||
DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
|
||||
Requires<[IsARM, CarryDefIsUnused]> {
|
||||
let Inst{4} = 1;
|
||||
|
|
@ -1145,14 +1145,14 @@ def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
|||
// FIXME: Allow these to be predicated.
|
||||
let Defs = [CPSR], Uses = [CPSR] in {
|
||||
def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
|
||||
DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
|
||||
DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
|
||||
Requires<[IsARM, CarryDefIsUnused]> {
|
||||
let Inst{20} = 1;
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
|
||||
DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
|
||||
DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
|
||||
Requires<[IsARM, CarryDefIsUnused]> {
|
||||
let Inst{4} = 1;
|
||||
|
|
@ -1193,7 +1193,7 @@ defm BIC : AsI1_bin_irs<0b1110, "bic",
|
|||
|
||||
def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
||||
AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
|
||||
"bfc", " $dst, $imm", "$src = $dst",
|
||||
"bfc", "\t$dst, $imm", "$src = $dst",
|
||||
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
|
||||
Requires<[IsARM, HasV6T2]> {
|
||||
let Inst{27-21} = 0b0111110;
|
||||
|
|
@ -1201,19 +1201,19 @@ def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
|||
}
|
||||
|
||||
def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
|
||||
"mvn", " $dst, $src",
|
||||
"mvn", "\t$dst, $src",
|
||||
[(set GPR:$dst, (not GPR:$src))]>, UnaryDP {
|
||||
let Inst{4} = 0;
|
||||
}
|
||||
def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
|
||||
IIC_iMOVsr, "mvn", " $dst, $src",
|
||||
IIC_iMOVsr, "mvn", "\t$dst, $src",
|
||||
[(set GPR:$dst, (not so_reg:$src))]>, UnaryDP {
|
||||
let Inst{4} = 1;
|
||||
let Inst{7} = 0;
|
||||
}
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
||||
def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
|
||||
IIC_iMOVi, "mvn", " $dst, $imm",
|
||||
IIC_iMOVi, "mvn", "\t$dst, $imm",
|
||||
[(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
|
||||
let Inst{25} = 1;
|
||||
}
|
||||
|
|
@ -1227,15 +1227,15 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm),
|
|||
|
||||
let isCommutable = 1 in
|
||||
def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, "mul", " $dst, $a, $b",
|
||||
IIC_iMUL32, "mul", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
|
||||
|
||||
def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
IIC_iMAC32, "mla", " $dst, $a, $b, $c",
|
||||
IIC_iMAC32, "mla", "\t$dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
|
||||
|
||||
def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
IIC_iMAC32, "mls", " $dst, $a, $b, $c",
|
||||
IIC_iMAC32, "mls", "\t$dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
|
||||
Requires<[IsARM, HasV6T2]>;
|
||||
|
||||
|
|
@ -1244,31 +1244,31 @@ let neverHasSideEffects = 1 in {
|
|||
let isCommutable = 1 in {
|
||||
def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
|
||||
(ins GPR:$a, GPR:$b), IIC_iMUL64,
|
||||
"smull", " $ldst, $hdst, $a, $b", []>;
|
||||
"smull", "\t$ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
|
||||
(ins GPR:$a, GPR:$b), IIC_iMUL64,
|
||||
"umull", " $ldst, $hdst, $a, $b", []>;
|
||||
"umull", "\t$ldst, $hdst, $a, $b", []>;
|
||||
}
|
||||
|
||||
// Multiply + accumulate
|
||||
def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
|
||||
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
||||
"smlal", " $ldst, $hdst, $a, $b", []>;
|
||||
"smlal", "\t$ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
|
||||
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
||||
"umlal", " $ldst, $hdst, $a, $b", []>;
|
||||
"umlal", "\t$ldst, $hdst, $a, $b", []>;
|
||||
|
||||
def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
|
||||
(ins GPR:$a, GPR:$b), IIC_iMAC64,
|
||||
"umaal", " $ldst, $hdst, $a, $b", []>,
|
||||
"umaal", "\t$ldst, $hdst, $a, $b", []>,
|
||||
Requires<[IsARM, HasV6]>;
|
||||
} // neverHasSideEffects
|
||||
|
||||
// Most significant word multiply
|
||||
def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, "smmul", " $dst, $a, $b",
|
||||
IIC_iMUL32, "smmul", "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
|
||||
Requires<[IsARM, HasV6]> {
|
||||
let Inst{7-4} = 0b0001;
|
||||
|
|
@ -1276,7 +1276,7 @@ def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
|||
}
|
||||
|
||||
def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
IIC_iMAC32, "smmla", " $dst, $a, $b, $c",
|
||||
IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
|
||||
Requires<[IsARM, HasV6]> {
|
||||
let Inst{7-4} = 0b0001;
|
||||
|
|
@ -1284,7 +1284,7 @@ def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|||
|
||||
|
||||
def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
IIC_iMAC32, "smmls", " $dst, $a, $b, $c",
|
||||
IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
|
||||
Requires<[IsARM, HasV6]> {
|
||||
let Inst{7-4} = 0b1101;
|
||||
|
|
@ -1292,7 +1292,7 @@ def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
|||
|
||||
multiclass AI_smul<string opc, PatFrag opnode> {
|
||||
def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, !strconcat(opc, "bb"), " $dst, $a, $b",
|
||||
IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
||||
(sext_inreg GPR:$b, i16)))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1301,7 +1301,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, !strconcat(opc, "bt"), " $dst, $a, $b",
|
||||
IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
|
||||
(sra GPR:$b, (i32 16))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1310,7 +1310,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, !strconcat(opc, "tb"), " $dst, $a, $b",
|
||||
IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
|
||||
(sext_inreg GPR:$b, i16)))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1319,7 +1319,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL32, !strconcat(opc, "tt"), " $dst, $a, $b",
|
||||
IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
|
||||
(sra GPR:$b, (i32 16))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1328,7 +1328,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL16, !strconcat(opc, "wb"), " $dst, $a, $b",
|
||||
IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sra (opnode GPR:$a,
|
||||
(sext_inreg GPR:$b, i16)), (i32 16)))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1337,7 +1337,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
IIC_iMUL16, !strconcat(opc, "wt"), " $dst, $a, $b",
|
||||
IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b",
|
||||
[(set GPR:$dst, (sra (opnode GPR:$a,
|
||||
(sra GPR:$b, (i32 16))), (i32 16)))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1349,7 +1349,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
|
|||
|
||||
multiclass AI_smla<string opc, PatFrag opnode> {
|
||||
def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
|
||||
IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc,
|
||||
(opnode (sext_inreg GPR:$a, i16),
|
||||
(sext_inreg GPR:$b, i16))))]>,
|
||||
|
|
@ -1359,7 +1359,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
|
||||
IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
|
||||
(sra GPR:$b, (i32 16)))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1368,7 +1368,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
|
||||
IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
|
||||
(sext_inreg GPR:$b, i16))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1377,16 +1377,16 @@ multiclass AI_smla<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
|
||||
(sra GPR:$b, (i32 16)))))]>,
|
||||
IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
|
||||
(sra GPR:$b, (i32 16)))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
let Inst{5} = 1;
|
||||
let Inst{6} = 1;
|
||||
}
|
||||
|
||||
def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
|
||||
IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
||||
(sext_inreg GPR:$b, i16)), (i32 16))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1395,7 +1395,7 @@ multiclass AI_smla<string opc, PatFrag opnode> {
|
|||
}
|
||||
|
||||
def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
|
||||
IIC_iMAC16, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
|
||||
IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc",
|
||||
[(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
|
||||
(sra GPR:$b, (i32 16))), (i32 16))))]>,
|
||||
Requires<[IsARM, HasV5TE]> {
|
||||
|
|
@ -1415,7 +1415,7 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
|
|||
//
|
||||
|
||||
def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
||||
"clz", " $dst, $src",
|
||||
"clz", "\t$dst, $src",
|
||||
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
|
||||
let Inst{7-4} = 0b0001;
|
||||
let Inst{11-8} = 0b1111;
|
||||
|
|
@ -1423,7 +1423,7 @@ def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|||
}
|
||||
|
||||
def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
||||
"rev", " $dst, $src",
|
||||
"rev", "\t$dst, $src",
|
||||
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
|
||||
let Inst{7-4} = 0b0011;
|
||||
let Inst{11-8} = 0b1111;
|
||||
|
|
@ -1431,7 +1431,7 @@ def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|||
}
|
||||
|
||||
def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
||||
"rev16", " $dst, $src",
|
||||
"rev16", "\t$dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(or (and (srl GPR:$src, (i32 8)), 0xFF),
|
||||
(or (and (shl GPR:$src, (i32 8)), 0xFF00),
|
||||
|
|
@ -1444,7 +1444,7 @@ def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|||
}
|
||||
|
||||
def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
||||
"revsh", " $dst, $src",
|
||||
"revsh", "\t$dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(sext_inreg
|
||||
(or (srl (and GPR:$src, 0xFF00), (i32 8)),
|
||||
|
|
@ -1457,7 +1457,7 @@ def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
|
|||
|
||||
def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
|
||||
(ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
||||
IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
|
||||
IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, LSL $shamt",
|
||||
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
|
||||
(and (shl GPR:$src2, (i32 imm:$shamt)),
|
||||
0xFFFF0000)))]>,
|
||||
|
|
@ -1474,7 +1474,7 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
|
|||
|
||||
def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
|
||||
(ins GPR:$src1, GPR:$src2, i32imm:$shamt),
|
||||
IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
|
||||
IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, ASR $shamt",
|
||||
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
|
||||
(and (sra GPR:$src2, imm16_31:$shamt),
|
||||
0xFFFF)))]>, Requires<[IsARM, HasV6]> {
|
||||
|
|
@ -1520,7 +1520,7 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
|
|||
// FIXME: should be able to write a pattern for ARMcmov, but can't use
|
||||
// a two-value operand where a dag node expects two operands. :(
|
||||
def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
|
||||
IIC_iCMOVr, "mov", " $dst, $true",
|
||||
IIC_iCMOVr, "mov", "\t$dst, $true",
|
||||
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
|
||||
RegConstraint<"$false = $dst">, UnaryDP {
|
||||
let Inst{4} = 0;
|
||||
|
|
@ -1529,7 +1529,7 @@ def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
|
|||
|
||||
def MOVCCs : AI1<0b1101, (outs GPR:$dst),
|
||||
(ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
|
||||
"mov", " $dst, $true",
|
||||
"mov", "\t$dst, $true",
|
||||
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
|
||||
RegConstraint<"$false = $dst">, UnaryDP {
|
||||
let Inst{4} = 1;
|
||||
|
|
@ -1539,7 +1539,7 @@ def MOVCCs : AI1<0b1101, (outs GPR:$dst),
|
|||
|
||||
def MOVCCi : AI1<0b1101, (outs GPR:$dst),
|
||||
(ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
|
||||
"mov", " $dst, $true",
|
||||
"mov", "\t$dst, $true",
|
||||
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
|
||||
RegConstraint<"$false = $dst">, UnaryDP {
|
||||
let Inst{25} = 1;
|
||||
|
|
@ -1554,7 +1554,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
|
|||
let isCall = 1,
|
||||
Defs = [R0, R12, LR, CPSR] in {
|
||||
def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
|
||||
"bl __aeabi_read_tp",
|
||||
"bl\t__aeabi_read_tp",
|
||||
[(set R0, ARMthread_pointer)]>;
|
||||
}
|
||||
|
||||
|
|
@ -1578,12 +1578,12 @@ let Defs =
|
|||
def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
|
||||
AddrModeNone, SizeSpecial, IndexModeNone,
|
||||
Pseudo, NoItinerary,
|
||||
"str sp, [$src, #+8] @ eh_setjmp begin\n\t"
|
||||
"add r12, pc, #8\n\t"
|
||||
"str r12, [$src, #+4]\n\t"
|
||||
"mov r0, #0\n\t"
|
||||
"add pc, pc, #0\n\t"
|
||||
"mov r0, #1 @ eh_setjmp end", "",
|
||||
"str\tsp, [$src, #+8] @ eh_setjmp begin\n\t"
|
||||
"add\tr12, pc, #8\n\t"
|
||||
"str\tr12, [$src, #+4]\n\t"
|
||||
"mov\tr0, #0\n\t"
|
||||
"add\tpc, pc, #0\n\t"
|
||||
"mov\tr0, #1 @ eh_setjmp end", "",
|
||||
[(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
|
||||
}
|
||||
|
||||
|
|
@ -1603,7 +1603,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|||
let isReMaterializable = 1 in
|
||||
def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
|
||||
Pseudo, IIC_iMOVi,
|
||||
"mov", " $dst, $src",
|
||||
"mov", "\t$dst, $src",
|
||||
[(set GPR:$dst, so_imm2part:$src)]>,
|
||||
Requires<[IsARM, NoV6T2]>;
|
||||
|
||||
|
|
@ -1626,7 +1626,7 @@ def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
|
|||
// FIXME: Remove this when we can do generalized remat.
|
||||
let isReMaterializable = 1 in
|
||||
def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
|
||||
"movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
|
||||
"movw", "\t$dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}",
|
||||
[(set GPR:$dst, (i32 imm:$src))]>,
|
||||
Requires<[IsARM, HasV6T2]>;
|
||||
|
||||
|
|
|
|||
|
|
@ -419,7 +419,7 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
|
|||
printSOImm(O, V1, VerboseAsm, MAI);
|
||||
O << "\n\torr";
|
||||
printPredicateOperand(MI, 2);
|
||||
O << " ";
|
||||
O << "\t";
|
||||
printOperand(MI, 0);
|
||||
O << ", ";
|
||||
printOperand(MI, 0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue