forked from OSchip/llvm-project
parent
5b112845da
commit
13db94540c
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@ -171,6 +171,20 @@ private:
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bool translateXor(const User &U) {
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return translateBinaryOp(TargetOpcode::G_XOR, U);
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}
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bool translateUDiv(const User &U) {
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return translateBinaryOp(TargetOpcode::G_UDIV, U);
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}
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bool translateSDiv(const User &U) {
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return translateBinaryOp(TargetOpcode::G_SDIV, U);
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}
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bool translateURem(const User &U) {
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return translateBinaryOp(TargetOpcode::G_UREM, U);
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}
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bool translateSRem(const User &U) {
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return translateBinaryOp(TargetOpcode::G_SREM, U);
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}
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bool translateAlloca(const User &U) {
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return translateStaticAlloca(cast<AllocaInst>(U));
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}
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@ -215,11 +229,7 @@ private:
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bool translateFAdd(const User &U) { return false; }
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bool translateFSub(const User &U) { return false; }
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bool translateFMul(const User &U) { return false; }
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bool translateUDiv(const User &U) { return false; }
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bool translateSDiv(const User &U) { return false; }
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bool translateFDiv(const User &U) { return false; }
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bool translateURem(const User &U) { return false; }
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bool translateSRem(const User &U) { return false; }
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bool translateFRem(const User &U) { return false; }
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bool translateGetElementPtr(const User &U) { return false; }
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bool translateFence(const User &U) { return false; }
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@ -107,6 +107,38 @@ def G_MUL : Instruction {
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let isCommutable = 1;
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}
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// Generic signed division.
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def G_SDIV : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src1, unknown:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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// Generic unsigned division.
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def G_UDIV : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src1, unknown:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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// Generic signed remainder.
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def G_SREM : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src1, unknown:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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// Generic unsigned remainder.
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def G_UREM : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src1, unknown:$src2);
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let hasSideEffects = 0;
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let isCommutable = 0;
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}
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// Generic addition consuming and producing a carry flag.
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def G_ADDE : Instruction {
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let OutOperandList = (outs unknown:$dst, unknown:$carry_out);
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@ -173,6 +173,18 @@ HANDLE_TARGET_OPCODE(G_SUB)
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// Generic multiply instruction.
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HANDLE_TARGET_OPCODE(G_MUL)
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// Generic signed division instruction.
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HANDLE_TARGET_OPCODE(G_SDIV)
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// Generic unsigned division instruction.
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HANDLE_TARGET_OPCODE(G_UDIV)
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// Generic signed remainder instruction.
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HANDLE_TARGET_OPCODE(G_SREM)
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// Generic unsigned remainder instruction.
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HANDLE_TARGET_OPCODE(G_UREM)
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/// Generic bitwise and instruction.
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HANDLE_TARGET_OPCODE(G_AND)
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@ -459,6 +459,50 @@ define i32 @test_ashr(i32 %arg1, i32 %arg2) {
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ret i32 %res
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}
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; CHECK-LABEL: name: test_sdiv
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; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
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; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SDIV s32 [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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define i32 @test_sdiv(i32 %arg1, i32 %arg2) {
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%res = sdiv i32 %arg1, %arg2
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ret i32 %res
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}
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; CHECK-LABEL: name: test_udiv
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; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
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; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UDIV s32 [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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define i32 @test_udiv(i32 %arg1, i32 %arg2) {
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%res = udiv i32 %arg1, %arg2
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ret i32 %res
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}
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; CHECK-LABEL: name: test_srem
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; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
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; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SREM s32 [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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define i32 @test_srem(i32 %arg1, i32 %arg2) {
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%res = srem i32 %arg1, %arg2
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ret i32 %res
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}
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; CHECK-LABEL: name: test_urem
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; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
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; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
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; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_UREM s32 [[ARG1]], [[ARG2]]
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; CHECK-NEXT: %w0 = COPY [[RES]]
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; CHECK-NEXT: RET_ReallyLR implicit %w0
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define i32 @test_urem(i32 %arg1, i32 %arg2) {
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%res = urem i32 %arg1, %arg2
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ret i32 %res
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}
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; CHECK-LABEL: name: test_constant_null
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; CHECK: [[NULL:%[0-9]+]](64) = G_CONSTANT p0 0
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; CHECK: %x0 = COPY [[NULL]]
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