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Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones). 

Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

llvm-svn: 28097
This commit is contained in:
Chris Lattner 2006-05-04 16:56:45 +00:00
parent 06041abeb6
commit 13d5f3eb05
2 changed files with 9 additions and 26 deletions
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14
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -102,9 +102,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@ -119,7 +118,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::STVX, 3)
.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
@ -137,9 +136,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11);
} else if (RC == PPC::GPRCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
} else if (RC == PPC::G8RCRegisterClass) {
@ -154,7 +152,7 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0);
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");

21
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
View File

@ -264,21 +264,6 @@ def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;
def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, CR3, CR4]>
{
let MethodProtos = [{
iterator allocation_order_begin(MachineFunction &MF) const;
iterator allocation_order_end(MachineFunction &MF) const;
}];
let MethodBodies = [{
CRRCClass::iterator
CRRCClass::allocation_order_begin(MachineFunction &MF) const {
return begin();
}
CRRCClass::iterator
CRRCClass::allocation_order_end(MachineFunction &MF) const {
return end()-3;
}
}];
}
def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
CR3, CR4]>;