forked from OSchip/llvm-project
[ELF] Implement option to force PIC compatible Thunks
By default LLD will generate position independent Thunks when the --pie or
--shared option is used. Reference to absolute addresses is permitted in
other cases. For some embedded systems position independent thunks are
needed for code that executes before the MMU has been set up. The option
--pic-veneer is used by ld.bfd to force position independent thunks.
The patch adds --pic-veneer as the option is needed for the Linux kernel
on Arm.
fixes pr39886
Differential Revision: https://reviews.llvm.org/D55505
llvm-svn: 351326
This commit is contained in:
Peter Smith
parent
3ec170c85a
commit
13d134684f
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@ -159,6 +159,7 @@ struct Configuration {
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bool OFormatBinary;
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bool Omagic;
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bool OptRemarksWithHotness;
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bool PicThunk;
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bool Pie;
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bool PrintGcSections;
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bool PrintIcfSections;
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@ -1006,6 +1006,7 @@ static void setConfigs(opt::InputArgList &Args) {
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Config->Endianness = Config->IsLE ? endianness::little : endianness::big;
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Config->IsMips64EL = (K == ELF64LEKind && M == EM_MIPS);
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Config->Pic = Config->Pie || Config->Shared;
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Config->PicThunk = Args.hasArg(OPT_pic_veneer, Config->Pic);
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Config->Wordsize = Config->Is64 ? 8 : 4;
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// ELF defines two different ways to store relocation addends as shown below:
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@ -255,6 +255,9 @@ defm use_android_relr_tags: B<"use-android-relr-tags",
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"Use SHT_ANDROID_RELR / DT_ANDROID_RELR* tags instead of SHT_RELR / DT_RELR*",
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"Use SHT_RELR / DT_RELR* tags (default)">;
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def pic_veneer: F<"pic-veneer">,
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HelpText<"Always generate position independent thunks (veneers)">;
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defm pie: B<"pie",
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"Create a position independent executable",
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"Do not create a position independent executable (default)">;
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@ -722,7 +722,7 @@ Thunk::~Thunk() = default;
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static Thunk *addThunkAArch64(RelType Type, Symbol &S) {
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if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
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fatal("unrecognized relocation type");
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if (Config->Pic)
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if (Config->PicThunk)
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return make<AArch64ADRPThunk>(S);
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return make<AArch64ABSLongThunk>(S);
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}
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@ -739,7 +739,7 @@ static Thunk *addThunkPreArmv7(RelType Reloc, Symbol &S) {
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case R_ARM_JUMP24:
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case R_ARM_CALL:
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case R_ARM_THM_CALL:
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if (Config->Pic)
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if (Config->PicThunk)
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return make<ARMV5PILongThunk>(S);
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return make<ARMV5ABSLongThunk>(S);
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}
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@ -794,13 +794,13 @@ static Thunk *addThunkArm(RelType Reloc, Symbol &S) {
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case R_ARM_PLT32:
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case R_ARM_JUMP24:
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case R_ARM_CALL:
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if (Config->Pic)
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if (Config->PicThunk)
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return make<ARMV7PILongThunk>(S);
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return make<ARMV7ABSLongThunk>(S);
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case R_ARM_THM_JUMP19:
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case R_ARM_THM_JUMP24:
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case R_ARM_THM_CALL:
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if (Config->Pic)
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if (Config->PicThunk)
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return make<ThumbV7PILongThunk>(S);
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return make<ThumbV7ABSLongThunk>(S);
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}
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@ -820,7 +820,7 @@ static Thunk *addThunkPPC64(RelType Type, Symbol &S) {
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if (S.isInPlt())
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return make<PPC64PltCallStub>(S);
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if (Config->Pic)
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if (Config->PicThunk)
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return make<PPC64PILongBranchThunk>(S);
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return make<PPC64PDLongBranchThunk>(S);
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@ -311,6 +311,8 @@ Write optimization remarks in YAML format to
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.Ar file .
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.It Fl -opt-remarks-with-hotness
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Include hotness information in the optimization remarks file.
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.It Fl -pic-veneer
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Always generate position independent thunks.
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.It Fl -pie
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Create a position independent executable.
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.It Fl -print-gc-sections
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@ -0,0 +1,87 @@
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// REQUIRES: arm
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// RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
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// RUN: echo "SECTIONS { \
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// RUN: . = SIZEOF_HEADERS; \
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// RUN: .text_low : { *(.text_low) *(.text_low2) } \
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// RUN: .text_high 0x2000000 : { *(.text_high) *(.text_high2) } \
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// RUN: } " > %t.script
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// RUN: ld.lld --pic-veneer --script %t.script %t -o %t2 2>&1
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// RUN: llvm-objdump -d -triple=thumbv7a-none-linux-gnueabi %t2 | FileCheck %s
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// Test that we can force generation of position independent thunks even when
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// inputs are not pic.
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.syntax unified
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.section .text_low, "ax", %progbits
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.thumb
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.globl _start
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_start: bx lr
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.globl low_target
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.type low_target, %function
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low_target:
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bl high_target
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bl high_target2
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.section .text_low2, "ax", %progbits
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.thumb
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.globl low_target2
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.type low_target2, %function
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low_target2:
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bl high_target
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bl high_target2
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// CHECK: Disassembly of section .text_low:
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// CHECK-NEXT: _start:
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// CHECK-NEXT: 94: 70 47 bx lr
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// CHECK: low_target:
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// CHECK-NEXT: 96: 00 f0 03 f8 bl #6
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// CHECK-NEXT: 9a: 00 f0 07 f8 bl #14
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// CHECK-NEXT: 9e: d4 d4 bmi #-88
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// CHECK: __ThumbV7PILongThunk_high_target:
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// CHECK-NEXT: a0: 4f f6 55 7c movw r12, #65365
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// CHECK-NEXT: a4: c0 f2 ff 1c movt r12, #511
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// CHECK-NEXT: a8: fc 44 add r12, pc
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// CHECK-NEXT: aa: 60 47 bx r12
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// CHECK: __ThumbV7PILongThunk_high_target2:
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// CHECK-NEXT: ac: 4f f6 69 7c movw r12, #65385
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// CHECK-NEXT: b0: c0 f2 ff 1c movt r12, #511
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// CHECK-NEXT: b4: fc 44 add r12, pc
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// CHECK-NEXT: b6: 60 47 bx r12
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// CHECK: low_target2:
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// CHECK-NEXT: b8: ff f7 f2 ff bl #-28
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// CHECK-NEXT: bc: ff f7 f6 ff bl #-20
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.section .text_high, "ax", %progbits
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.thumb
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.globl high_target
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.type high_target, %function
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high_target:
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bl low_target
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bl low_target2
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.section .text_high2, "ax", %progbits
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.thumb
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.globl high_target2
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.type high_target2, %function
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high_target2:
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bl low_target
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bl low_target2
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// CHECK: Disassembly of section .text_high:
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// CHECK-NEXT: high_target:
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// CHECK-NEXT: 2000000: 00 f0 02 f8 bl #4
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// CHECK-NEXT: 2000004: 00 f0 06 f8 bl #12
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// CHECK: __ThumbV7PILongThunk_low_target:
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// CHECK-NEXT: 2000008: 40 f2 83 0c movw r12, #131
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// CHECK-NEXT: 200000c: cf f6 00 6c movt r12, #65024
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// CHECK-NEXT: 2000010: fc 44 add r12, pc
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// CHECK-NEXT: 2000012: 60 47 bx r12
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// CHECK: __ThumbV7PILongThunk_low_target2:
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// CHECK-NEXT: 2000014: 40 f2 99 0c movw r12, #153
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// CHECK-NEXT: 2000018: cf f6 00 6c movt r12, #65024
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// CHECK-NEXT: 200001c: fc 44 add r12, pc
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// CHECK-NEXT: 200001e: 60 47 bx r12
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// CHECK: high_target2:
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// CHECK-NEXT: 2000020: ff f7 f2 ff bl #-28
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// CHECK-NEXT: 2000024: ff f7 f6 ff bl #-20
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