forked from OSchip/llvm-project
[IRTranslator] Refactor to expose a translateBinaryOp method.
This method will be used for every binary operation. NFC. llvm-svn: 272431
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@ -87,12 +87,20 @@ private:
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// Note: we would need to do something so that we can recognize such operand
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// as constants.
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// 3. Create the generic instruction.
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bool translateADD(const Instruction &Inst);
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bool translateBr(const Instruction &Inst);
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bool translateReturn(const Instruction &Inst);
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/// Translate \p Inst into a binary operation \p Opcode.
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/// Insert the newly translated instruction right where the MIRBuilder
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/// is set.
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///
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/// \pre \p Inst is a binary operation.
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///
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/// \return true if the translation succeeded.
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bool translateBinaryOp(unsigned Opcode, const Instruction &Inst);
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// Builder for machine instruction a la IRBuilder.
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// I.e., compared to regular MIBuilder, this one also inserts the instruction
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// in the current block, it can creates block, etc., basically a kind of
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@ -61,7 +61,7 @@ MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
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return *MBB;
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}
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bool IRTranslator::translateADD(const Instruction &Inst) {
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bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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@ -69,7 +69,7 @@ bool IRTranslator::translateADD(const Instruction &Inst) {
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unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
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unsigned Res = getOrCreateVReg(Inst);
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MIRBuilder.buildInstr(TargetOpcode::G_ADD, Inst.getType(), Res, Op0, Op1);
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MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1);
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return true;
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}
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@ -103,7 +103,7 @@ bool IRTranslator::translate(const Instruction &Inst) {
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MIRBuilder.setDebugLoc(Inst.getDebugLoc());
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switch(Inst.getOpcode()) {
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case Instruction::Add:
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return translateADD(Inst);
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return translateBinaryOp(TargetOpcode::G_ADD, Inst);
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case Instruction::Br:
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return translateBr(Inst);
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case Instruction::Ret:
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