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[X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in the scheduler models as much as possible. NFCI 

This reduces the total number of generated scheduler classes from 5404 to 5316.

llvm-svn: 327815
This commit is contained in:
Craig Topper 2018-03-19 00:56:09 +00:00
parent a35ee70641
commit 13a1650d8a
5 changed files with 473 additions and 945 deletions
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282
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -599,8 +599,7 @@ def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC8rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADCX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "ADOX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "BT(16|32|64)ri8")>;
@ -619,24 +618,17 @@ def: InstRW<[BWWriteResGroup6], (instregex "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|
def: InstRW<[BWWriteResGroup6], (instregex "JMP_1")>;
def: InstRW<[BWWriteResGroup6], (instregex "JMP_4")>;
def: InstRW<[BWWriteResGroup6], (instregex "RORX(32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR8ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SARX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB8rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL8ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHLX(32|64)rr")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR8r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR8ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup6], (instregex "SHRX(32|64)rr")>;
def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
@ -859,48 +851,35 @@ def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "ADD8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "AND8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "CBW")>;
def: InstRW<[BWWriteResGroup9], (instregex "CLC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMC")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "CMP8rr")>;
def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
def: InstRW<[BWWriteResGroup9], (instregex "DEC(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "DEC8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "DEC(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOV8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[BWWriteResGroup9], (instregex "MOVZX(16|32|64)rr8")>;
def: InstRW<[BWWriteResGroup9], (instregex "NEG(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NEG8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOOP")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT(16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT8r")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "NOT(8|16|32|64)r")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "OR8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SAHF")>;
def: InstRW<[BWWriteResGroup9], (instregex "SGDT64m")>;
def: InstRW<[BWWriteResGroup9], (instregex "SIDT64m")>;
@ -908,22 +887,17 @@ def: InstRW<[BWWriteResGroup9], (instregex "SLDT64m")>;
def: InstRW<[BWWriteResGroup9], (instregex "SMSW16m")>;
def: InstRW<[BWWriteResGroup9], (instregex "STC")>;
def: InstRW<[BWWriteResGroup9], (instregex "STRm")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "SUB8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "SYSCALL")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "TEST8rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8i8")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8ri")>;
def: InstRW<[BWWriteResGroup9], (instregex "XOR8rr")>;
def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
let Latency = 1;
@ -1027,14 +1001,10 @@ def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROL(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROL8r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROL8ri")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR8r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR8ri")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup13], (instregex "ROR(8|16|32|64)ri")>;
def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
let Latency = 2;
@ -1362,8 +1332,7 @@ def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[BWWriteResGroup30], (instregex "XADD(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup30], (instregex "XADD8rr")>;
def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr")>;
def: InstRW<[BWWriteResGroup30], (instregex "XCHG8rr")>;
def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
@ -1429,30 +1398,21 @@ def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCL(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCL8r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCL8ri")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR(16|32|64)ri")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR8r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR8ri")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)ri")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR(8|16|32|64)r1")>;
def: InstRW<[BWWriteResGroup35], (instregex "RCR(8|16|32|64)ri")>;
def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[BWWriteResGroup36], (instregex "ROL(16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "ROL8rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "ROR(16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "ROR8rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SAR(16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SAR8rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHL(16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHL8rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHR(16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHR8rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "ROR(8|16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SAR(8|16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHL(8|16|32|64)rCL")>;
def: InstRW<[BWWriteResGroup36], (instregex "SHR(8|16|32|64)rCL")>;
def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
let Latency = 3;
@ -2000,16 +1960,14 @@ def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup63], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADC8rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADCX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "ADOX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup63], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "RORX(32|64)mi")>;
def: InstRW<[BWWriteResGroup63], (instregex "SARX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SBB8rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SBB(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SHLX(32|64)rm")>;
def: InstRW<[BWWriteResGroup63], (instregex "SHRX(32|64)rm")>;
@ -2175,27 +2133,18 @@ def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup66], (instregex "ADD(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "ADD8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "AND(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "AND8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP8mi")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP8mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "OR(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "OR8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "AND(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "CMP(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[BWWriteResGroup66], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "SUB8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "SUB(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST8mi")>;
def: InstRW<[BWWriteResGroup66], (instregex "TEST8mr")>;
def: InstRW<[BWWriteResGroup66], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "XOR8rm")>;
def: InstRW<[BWWriteResGroup66], (instregex "XOR(8|16|32|64)rm")>;
def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 6;
@ -2220,54 +2169,34 @@ def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup69], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup69], (instregex "BTS(16|32|64)mi8")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR8m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR8mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL8m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL8mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR8m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR8mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL(8|16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHL(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR(8|16|32|64)m1")>;
def: InstRW<[BWWriteResGroup69], (instregex "SHR(8|16|32|64)mi")>;
def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "DEC(16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "DEC8m")>;
def: InstRW<[BWWriteResGroup70], (instregex "INC(16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "INC8m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NEG(16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NEG8m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NOT(16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NOT8m")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "AND(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "DEC(8|16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "INC(8|16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NEG(8|16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "NOT(8|16|32|64)m")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[BWWriteResGroup70], (instregex "PUSH(16|32|64)rmm")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR8mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR8mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "SUB(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup70], (instregex "XOR(8|16|32|64)mr")>;
def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
let Latency = 6;
@ -2738,54 +2667,39 @@ def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]>
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCL(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCL8m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCL8mi")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR8m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR8mi")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR(8|16|32|64)m1")>;
def: InstRW<[BWWriteResGroup97], (instregex "RCR(8|16|32|64)mi")>;
def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
let ResourceCycles = [1,1,2,1];
}
def: InstRW<[BWWriteResGroup98], (instregex "ROR(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup98], (instregex "ROR8mCL")>;
def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[BWWriteResGroup99], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "ADC8mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "XCHG(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup99], (instregex "XCHG8rm")>;
def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[BWWriteResGroup100], (instregex "ADC(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "ADC8mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG8rm")>;
def: InstRW<[BWWriteResGroup100], (instregex "ROL(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "ROL8mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SAR8mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB8mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB8mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHL(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHL8mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHR(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHR8mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "CMPXCHG(8|16|32|64)rm")>;
def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SAR(8|16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB(8|16|32|64)mi")>;
def: InstRW<[BWWriteResGroup100], (instregex "SBB(8|16|32|64)mr")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHL(8|16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup100], (instregex "SHR(8|16|32|64)mCL")>;
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 9;
@ -3313,8 +3227,7 @@ def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPo
let NumMicroOps = 10;
let ResourceCycles = [1,1,1,4,1,2];
}
def: InstRW<[BWWriteResGroup149], (instregex "RCL(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup149], (instregex "RCL8mCL")>;
def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 16;
@ -3401,8 +3314,7 @@ def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPo
let NumMicroOps = 11;
let ResourceCycles = [2,1,1,3,1,3];
}
def: InstRW<[BWWriteResGroup160], (instregex "RCR(16|32|64)mCL")>;
def: InstRW<[BWWriteResGroup160], (instregex "RCR8mCL")>;
def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
let Latency = 19;
@ -3688,36 +3600,30 @@ def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0
let NumMicroOps = 8;
let ResourceCycles = [2,2,2,1,1];
}
def: InstRW<[BWWriteResGroup190], (instregex "DIV(16|32|64)m")>;
def: InstRW<[BWWriteResGroup190], (instregex "DIV8m")>;
def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
let Latency = 34;
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)ri")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN(16|32)rr")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN8ri")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN8rr")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri")>;
def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)rr")>;
def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
let Latency = 35;
let NumMicroOps = 8;
let ResourceCycles = [2,2,2,1,1];
}
def: InstRW<[BWWriteResGroup193], (instregex "IDIV(16|32|64)m")>;
def: InstRW<[BWWriteResGroup193], (instregex "IDIV8m")>;
def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)ir")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT(16|32)rr")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT8ir")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT8rr")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir")>;
def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)rr")>;
def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
let Latency = 40;

300
llvm/lib/Target/X86/X86SchedHaswell.td
View File

@ -1037,21 +1037,15 @@ def: InstRW<[HWWriteResGroup7], (instregex "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|
def: InstRW<[HWWriteResGroup7], (instregex "JMP_1")>;
def: InstRW<[HWWriteResGroup7], (instregex "JMP_4")>;
def: InstRW<[HWWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
@ -1274,48 +1268,35 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "AND8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr")>;
def: InstRW<[HWWriteResGroup10], (instrs CWDE)>;
def: InstRW<[HWWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
def: InstRW<[HWWriteResGroup10], (instregex "NEG(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "OR8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
@ -1323,22 +1304,17 @@ def: InstRW<[HWWriteResGroup10], (instregex "SLDT64m")>;
def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>;
def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
let Latency = 6;
@ -1877,27 +1853,18 @@ def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup18], (instregex "ADD(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP8mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "OR(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "ADD(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "AND(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "CMP(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "SUB(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>;
def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>;
def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>;
def: InstRW<[HWWriteResGroup18], (instregex "XOR(8|16|32|64)rm")>;
def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
let Latency = 2;
@ -1973,54 +1940,34 @@ def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[HWWriteResGroup25], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[HWWriteResGroup25], (instregex "BTS(16|32|64)mi8")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR8m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR8mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL8m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL8mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR8m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR8mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHL(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup25], (instregex "SHR(8|16|32|64)mi")>;
def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 7;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "DEC(16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "DEC8m")>;
def: InstRW<[HWWriteResGroup26], (instregex "INC(16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "INC8m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NEG(16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "ADD(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "AND(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "DEC(8|16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "INC(8|16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NEG(8|16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "NOT(8|16|32|64)m")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[HWWriteResGroup26], (instregex "PUSH(16|32|64)rmm")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "SUB(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup26], (instregex "XOR(8|16|32|64)mr")>;
def HWWriteResGroup27 : SchedWriteRes<[HWPort5]> {
let Latency = 2;
@ -2058,14 +2005,10 @@ def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [2];
}
def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROL8r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROL8ri")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR8r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR8ri")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup29], (instregex "ROR(8|16|32|64)ri")>;
def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
let Latency = 2;
@ -2145,19 +2088,15 @@ def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "ADC8rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instrs CWD)>;
def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
def: InstRW<[HWWriteResGroup35], (instregex "SBB8rr")>;
def: InstRW<[HWWriteResGroup35], (instregex "SET(A|BE)r")>;
def HWWriteResGroup36 : SchedWriteRes<[HWPort5,HWPort23]> {
@ -2269,11 +2208,9 @@ def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[HWWriteResGroup43], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "ADC8rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "SBB8rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "SBB(8|16|32|64)rm")>;
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
let Latency = 3;
@ -2295,22 +2232,17 @@ def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROL8m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROL8mi")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR8m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR8mi")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup46], (instregex "ROR(8|16|32|64)mi")>;
def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup47], (instregex "XADD(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup47], (instregex "XADD8rm")>;
def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>;
def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
let Latency = 8;
@ -2577,8 +2509,7 @@ def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[HWWriteResGroup54], (instregex "XADD(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup54], (instregex "XADD8rr")>;
def: InstRW<[HWWriteResGroup54], (instregex "XADD(8|16|32|64)rr")>;
def: InstRW<[HWWriteResGroup54], (instregex "XCHG8rr")>;
def HWWriteResGroup55 : SchedWriteRes<[HWPort0,HWPort5]> {
@ -2645,30 +2576,21 @@ def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
let ResourceCycles = [1,2];
}
def: InstRW<[HWWriteResGroup59], (instregex "CMOV(A|BE)(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL8r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL8ri")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)ri")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR8r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR8ri")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)ri")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR(8|16|32|64)r1")>;
def: InstRW<[HWWriteResGroup59], (instregex "RCR(8|16|32|64)ri")>;
def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
def: InstRW<[HWWriteResGroup60], (instregex "ROL(16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "ROL8rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "ROR(16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "ROR8rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SAR(16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SAR8rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHL(16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHL8rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHR(16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHR8rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "ROL(8|16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "ROR(8|16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SAR(8|16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHL(8|16|32|64)rCL")>;
def: InstRW<[HWWriteResGroup60], (instregex "SHR(8|16|32|64)rCL")>;
def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
let Latency = 4;
@ -2763,54 +2685,39 @@ def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]>
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCL8m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCL8mi")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR8m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR8mi")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR(8|16|32|64)m1")>;
def: InstRW<[HWWriteResGroup66], (instregex "RCR(8|16|32|64)mi")>;
def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 5;
let ResourceCycles = [1,1,2,1];
}
def: InstRW<[HWWriteResGroup67], (instregex "ROR(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup67], (instregex "ROR8mCL")>;
def: InstRW<[HWWriteResGroup67], (instregex "ROR(8|16|32|64)mCL")>;
def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "XCHG(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup68], (instregex "XCHG8rm")>;
def: InstRW<[HWWriteResGroup68], (instregex "ADC(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>;
def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[HWWriteResGroup69], (instregex "ADC(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "ADC8mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG8rm")>;
def: InstRW<[HWWriteResGroup69], (instregex "ROL(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHL(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHL8mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHR(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHR8mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SAR(8|16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB(8|16|32|64)mi")>;
def: InstRW<[HWWriteResGroup69], (instregex "SBB(8|16|32|64)mr")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHL(8|16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup69], (instregex "SHR(8|16|32|64)mCL")>;
def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
let Latency = 4;
@ -3335,8 +3242,7 @@ def HWWriteResGroup101 : SchedWriteRes<[HWPort06,HWPort0156]> {
let NumMicroOps = 5;
let ResourceCycles = [2,3];
}
def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG8rr")>;
def: InstRW<[HWWriteResGroup101], (instregex "CMPXCHG(8|16|32|64)rr")>;
def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
let Latency = 6;
@ -3533,8 +3439,7 @@ def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPo
let NumMicroOps = 10;
let ResourceCycles = [1,1,1,4,1,2];
}
def: InstRW<[HWWriteResGroup120], (instregex "RCL(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup120], (instregex "RCL8mCL")>;
def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>;
def HWWriteResGroup121 : SchedWriteRes<[HWPort0]> {
let Latency = 11;
@ -3665,8 +3570,7 @@ def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPo
let NumMicroOps = 11;
let ResourceCycles = [2,1,1,3,1,3];
}
def: InstRW<[HWWriteResGroup135], (instregex "RCR(16|32|64)mCL")>;
def: InstRW<[HWWriteResGroup135], (instregex "RCR8mCL")>;
def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>;
def HWWriteResGroup136 : SchedWriteRes<[HWPort0]> {
let Latency = 14;
@ -3955,20 +3859,16 @@ def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)ri")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN(16|32)rr")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN8ri")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN8rr")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri")>;
def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)rr")>;
def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 36;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)ir")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT(16|32)rr")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT8ir")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT8rr")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir")>;
def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)rr")>;
def HWWriteResGroup172 : SchedWriteRes<[HWPort01,HWPort15,HWPort015,HWPort0156]> {
let Latency = 31;

234
llvm/lib/Target/X86/X86SchedSandyBridge.td
View File

@ -468,15 +468,11 @@ def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>;
def: InstRW<[SBWriteResGroup4], (instregex "CQO")>;
def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>;
def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>;
def: InstRW<[SBWriteResGroup4], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL(16|32|64)r1")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHL(8|16|32|64)r1")>;
def: InstRW<[SBWriteResGroup4], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>;
def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>;
def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>;
@ -656,33 +652,24 @@ def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "CBW")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMC")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>;
def: InstRW<[SBWriteResGroup6], (instrs CWDE)>;
def: InstRW<[SBWriteResGroup6], (instregex "DEC(16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>;
def: InstRW<[SBWriteResGroup6], (instregex "INC(16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>;
def: InstRW<[SBWriteResGroup6], (instregex "DEC(8|16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOV(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;
@ -691,40 +678,31 @@ def: InstRW<[SBWriteResGroup6], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[SBWriteResGroup6], (instregex "MOVZX(16|32|64)rr8")>;
def: InstRW<[SBWriteResGroup6], (instregex "NEG(16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "NOT(8|16|32|64)r")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "STC")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR8i8")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>;
def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>;
def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
let Latency = 2;
@ -750,10 +728,8 @@ def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
}
def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>;
def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROL(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROR(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "ROR(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup9], (instregex "SET(A|BE)r")>;
def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>;
def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>;
@ -867,15 +843,11 @@ def SBWriteResGroup19 : SchedWriteRes<[SBPort05,SBPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB(8|16|32|64)ri")>;
def: InstRW<[SBWriteResGroup19], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[SBWriteResGroup19], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[SBWriteResGroup19], (instregex "SHRD(16|32|64)rri8")>;
@ -1043,16 +1015,11 @@ def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "ROL8rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "ROR(16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "ROR8rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SAR(16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SAR8rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHL(16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHL8rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHR(16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHR8rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "ROR(8|16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SAR(8|16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHL(8|16|32|64)rCL")>;
def: InstRW<[SBWriteResGroup23_2], (instregex "SHR(8|16|32|64)rCL")>;
def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
let Latency = 3;
@ -1216,8 +1183,7 @@ def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup31], (instregex "MOV(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup31], (instregex "MOV8rm")>;
def: InstRW<[SBWriteResGroup31], (instregex "MOV(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm16")>;
def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm32")>;
def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm8")>;
@ -1252,8 +1218,7 @@ def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup33], (instregex "MOV(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup33], (instregex "MOV8mr")>;
def: InstRW<[SBWriteResGroup33], (instregex "MOV(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup33], (instregex "MOVAPDmr")>;
def: InstRW<[SBWriteResGroup33], (instregex "MOVAPSmr")>;
def: InstRW<[SBWriteResGroup33], (instregex "MOVDQAmr")>;
@ -1406,8 +1371,7 @@ def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG8rr")>;
def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG(8|16|32|64)rr")>;
def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 5;
@ -1527,24 +1491,16 @@ def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup52], (instregex "ADD(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP8mr")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "ADD(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "AND(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup52], (instregex "CMP(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "LODSL")>;
def: InstRW<[SBWriteResGroup52], (instregex "LODSQ")>;
def: InstRW<[SBWriteResGroup52], (instregex "OR(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "OR8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "SUB8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "XOR8rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "SUB(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup52], (instregex "XOR(8|16|32|64)rm")>;
def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 6;
@ -1872,11 +1828,9 @@ def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup65], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "ADC8rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "SBB8rm")>;
def: InstRW<[SBWriteResGroup65], (instregex "SBB(8|16|32|64)rm")>;
def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
let Latency = 7;
@ -1909,51 +1863,32 @@ def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[SBWriteResGroup69], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[SBWriteResGroup69], (instregex "BTS(16|32|64)mi8")>;
def: InstRW<[SBWriteResGroup69], (instregex "SAR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SAR8mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL(16|32|64)m1")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL8m1")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL8mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHR8mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL(8|16|32|64)m1")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHL(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup69], (instregex "SHR(8|16|32|64)mi")>;
def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 7;
let NumMicroOps = 4;
let ResourceCycles = [1,2,1];
}
def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "DEC(16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "DEC8m")>;
def: InstRW<[SBWriteResGroup70], (instregex "INC(16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "INC8m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NEG(16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "ADD(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "AND(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "DEC(8|16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "INC(8|16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NEG(8|16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "NOT(8|16|32|64)m")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "SUB(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup70], (instregex "XOR(8|16|32|64)mr")>;
def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 8;
@ -2094,8 +2029,7 @@ def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> {
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG8rm")>;
def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16|32|64)rm")>;
def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let Latency = 8;
@ -2126,10 +2060,8 @@ def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let NumMicroOps = 5;
let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup85], (instregex "ROL(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup85], (instregex "ROL8mi")>;
def: InstRW<[SBWriteResGroup85], (instregex "ROR(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup85], (instregex "ROR8mi")>;
def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup85], (instregex "ROR(8|16|32|64)mi")>;
def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 8;
@ -2140,8 +2072,7 @@ def: InstRW<[SBWriteResGroup86], (instregex "MOVSB")>;
def: InstRW<[SBWriteResGroup86], (instrs MOVSL)>;
def: InstRW<[SBWriteResGroup86], (instregex "MOVSQ")>;
def: InstRW<[SBWriteResGroup86], (instregex "MOVSW")>;
def: InstRW<[SBWriteResGroup86], (instregex "XADD(16|32|64)rm")>;
def: InstRW<[SBWriteResGroup86], (instregex "XADD8rm")>;
def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 8;
@ -2340,36 +2271,27 @@ def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let NumMicroOps = 6;
let ResourceCycles = [1,2,3];
}
def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "ROL8mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "ROR(16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "ROR8mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SAR8mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHL(16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHL8mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHR(16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHR8mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "ROR(8|16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SAR(8|16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHL(8|16|32|64)mCL")>;
def: InstRW<[SBWriteResGroup97_2], (instregex "SHR(8|16|32|64)mCL")>;
def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,3];
}
def: InstRW<[SBWriteResGroup98], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "ADC(8|16|32|64)mi")>;
def: InstRW<[SBWriteResGroup98], (instregex "SBB(8|16|32|64)mi")>;
def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup99], (instregex "ADC(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup99], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup99], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[SBWriteResGroup99], (instregex "SBB8mr")>;
def: InstRW<[SBWriteResGroup99], (instregex "ADC(8|16|32|64)mr")>;
def: InstRW<[SBWriteResGroup99], (instregex "SBB(8|16|32|64)mr")>;
def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;

305
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

@ -703,8 +703,7 @@ def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC8rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADCX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "ADOX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
@ -724,24 +723,17 @@ def: InstRW<[SKLWriteResGroup7], (instregex "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS
def: InstRW<[SKLWriteResGroup7], (instregex "JMP_1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "JMP_4")>;
def: InstRW<[SKLWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB8rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL8ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR8ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def: InstRW<[SKLWriteResGroup7], (instregex "STAC")>;
@ -853,48 +845,35 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "ADD8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "AND8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "CMP8rr")>;
def: InstRW<[SKLWriteResGroup10], (instrs CWDE)>;
def: InstRW<[SKLWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[SKLWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NEG(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NEG8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "OR8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SIDT64m")>;
@ -902,22 +881,17 @@ def: InstRW<[SKLWriteResGroup10], (instregex "SLDT64m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKLWriteResGroup10], (instregex "STRm")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SUB8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKLWriteResGroup10], (instregex "XOR8rr")>;
def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
let Latency = 1;
@ -929,9 +903,8 @@ def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64from64rm")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVD64mr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVNTQmr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MMX_MOVQ64mr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOV(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOV(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mi")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOV8mr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPDmr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOVAPSmr")>;
def: InstRW<[SKLWriteResGroup11], (instregex "MOVDQAmr")>;
@ -1050,14 +1023,10 @@ def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
let ResourceCycles = [2];
}
def: InstRW<[SKLWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL8r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL8ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR8r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR8ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup15], (instregex "ROR(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup15], (instregex "SET(A|BE)r")>;
def SKLWriteResGroup16 : SchedWriteRes<[SKLPort015]> {
@ -1315,24 +1284,18 @@ def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SKLWriteResGroup33], (instregex "ROL(16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "ROL8rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "ROR(16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "ROR8rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SAR(16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SAR8rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHL(16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHL8rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHR(16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHR8rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "ROR(8|16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SAR(8|16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHL(8|16|32|64)rCL")>;
def: InstRW<[SKLWriteResGroup33], (instregex "SHR(8|16|32|64)rCL")>;
def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
let Latency = 3;
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SKLWriteResGroup34], (instregex "XADD(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup34], (instregex "XADD8rr")>;
def: InstRW<[SKLWriteResGroup34], (instregex "XADD(8|16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup34], (instregex "XCHG8rr")>;
def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
@ -1411,14 +1374,10 @@ def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCL(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCL8r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCL8ri")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR(16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR8r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR8ri")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)ri")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR(8|16|32|64)r1")>;
def: InstRW<[SKLWriteResGroup42], (instregex "RCR(8|16|32|64)ri")>;
def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
let Latency = 3;
@ -1688,9 +1647,8 @@ def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVD64to64rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MMX_MOVQ64rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOV(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOV(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOV64toPQIrm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOV8rm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOVDDUPrm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOVDI2PDIrm")>;
def: InstRW<[SKLWriteResGroup58], (instregex "MOVQI2PQIrm")>;
@ -1779,8 +1737,7 @@ def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
let NumMicroOps = 5;
let ResourceCycles = [2,3];
}
def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(16|32|64)rr")>;
def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG8rr")>;
def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
let Latency = 5;
@ -1979,8 +1936,7 @@ def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup74], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADC8rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADCX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "ADOX(32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
@ -1989,8 +1945,7 @@ def: InstRW<[SKLWriteResGroup74], (instregex "RORX32mi")>;
def: InstRW<[SKLWriteResGroup74], (instregex "RORX64mi")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SARX32rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SARX64rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SBB8rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SBB(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHLX32rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHLX64rm")>;
def: InstRW<[SKLWriteResGroup74], (instregex "SHRX32rm")>;
@ -2013,27 +1968,18 @@ def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup76], (instregex "ADD(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "ADD8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "AND8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mi")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP8mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "OR(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "OR8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "ADD(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "AND(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "CMP(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "SUB8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "SUB(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mi")>;
def: InstRW<[SKLWriteResGroup76], (instregex "TEST8mr")>;
def: InstRW<[SKLWriteResGroup76], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "XOR8rm")>;
def: InstRW<[SKLWriteResGroup76], (instregex "XOR(8|16|32|64)rm")>;
def SKLWriteResGroup77 : SchedWriteRes<[SKLPort5,SKLPort01]> {
let Latency = 6;
@ -2091,54 +2037,34 @@ def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]
def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup82], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup82], (instregex "BTS(16|32|64)mi8")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR8m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR8mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL8m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL8mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR8m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR8mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHL(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup82], (instregex "SHR(8|16|32|64)mi")>;
def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "DEC(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "DEC8m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "INC(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "INC8m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NEG(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NEG8m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NOT8m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "ADD(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "AND(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "DEC(8|16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "INC(8|16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NEG(8|16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "NOT(8|16|32|64)m")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[SKLWriteResGroup83], (instregex "PUSH(16|32|64)rmm")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR8mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "SUB(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup83], (instregex "XOR(8|16|32|64)mr")>;
def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 6;
@ -2494,22 +2420,17 @@ def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROL8m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROL8mi")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR8m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR8mi")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup100], (instregex "ROR(8|16|32|64)mi")>;
def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup101], (instregex "XADD(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup101], (instregex "XADD8rm")>;
def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 7;
@ -2573,7 +2494,7 @@ def: InstRW<[SKLWriteResGroup107], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL
def: InstRW<[SKLWriteResGroup107], (instrs IMUL8m)>;
def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instrs MUL64m)>;
def: InstRW<[SKLWriteResGroup107], (instregex "MUL8m")>;
def: InstRW<[SKLWriteResGroup107], (instrs MUL8m)>;
def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "PEXT(32|64)rm")>;
def: InstRW<[SKLWriteResGroup107], (instregex "POPCNT(16|32|64)rm")>;
@ -2775,58 +2696,44 @@ def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
let NumMicroOps = 5;
let ResourceCycles = [1,1,3];
}
def: InstRW<[SKLWriteResGroup115], (instregex "ROR(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup115], (instregex "ROR8mCL")>;
def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCL8m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCL8mi")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR8m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR8mi")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR(8|16|32|64)m1")>;
def: InstRW<[SKLWriteResGroup116], (instregex "RCR(8|16|32|64)mi")>;
def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKLWriteResGroup117], (instregex "ROL(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "ROL8mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SAR8mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHL(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHL8mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHR(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHR8mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SAR(8|16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHL(8|16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup117], (instregex "SHR(8|16|32|64)mCL")>;
def SKLWriteResGroup118 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKLWriteResGroup118], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup118], (instregex "ADC8mi")>;
def: InstRW<[SKLWriteResGroup118], (instregex "ADC(8|16|32|64)mi")>;
def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKLWriteResGroup119], (instregex "ADC(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "ADC8mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG8rm")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mi")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB8mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mr")>;
def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB(8|16|32|64)mi")>;
def: InstRW<[SKLWriteResGroup119], (instregex "SBB(8|16|32|64)mr")>;
def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 9;
@ -3155,8 +3062,7 @@ def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,
let NumMicroOps = 8;
let ResourceCycles = [1,1,1,1,1,3];
}
def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(16|32|64)rm")>;
def: InstRW<[SKLWriteResGroup143], (instregex "XCHG8rm")>;
def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
def SKLWriteResGroup144 : SchedWriteRes<[SKLPort05,SKLPort0156]> {
let Latency = 10;
@ -3473,8 +3379,7 @@ def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06
let NumMicroOps = 10;
let ResourceCycles = [1,1,1,5,1,1];
}
def: InstRW<[SKLWriteResGroup174], (instregex "RCL(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup174], (instregex "RCL8mCL")>;
def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
def SKLWriteResGroup175 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 16;
@ -3563,8 +3468,7 @@ def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06
let NumMicroOps = 11;
let ResourceCycles = [2,1,1,4,1,2];
}
def: InstRW<[SKLWriteResGroup185], (instregex "RCR(16|32|64)mCL")>;
def: InstRW<[SKLWriteResGroup185], (instregex "RCR8mCL")>;
def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 19;
@ -3766,8 +3670,7 @@ def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156
let NumMicroOps = 8;
let ResourceCycles = [2,4,1,1];
}
def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(16|32|64)m")>;
def: InstRW<[SKLWriteResGroup207], (instregex "IDIV8m")>;
def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 30;
@ -3782,20 +3685,16 @@ def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,S
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)ri")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN(16|32)rr")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN8ri")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN8rr")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri")>;
def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)rr")>;
def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)ir")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT(16|32)rr")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT8ir")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT8rr")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir")>;
def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)rr")>;
def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
let Latency = 37;

297
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

@ -1007,8 +1007,7 @@ def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC8rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADC(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADCX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "ADOX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
@ -1028,24 +1027,17 @@ def: InstRW<[SKXWriteResGroup7], (instregex "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS
def: InstRW<[SKXWriteResGroup7], (instregex "JMP_1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "JMP_4")>;
def: InstRW<[SKXWriteResGroup7], (instregex "RORX(32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR8ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SAR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SARX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB8rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SBB(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL8ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHL(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHLX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR8r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR8ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup7], (instregex "SHRX(32|64)rr")>;
def: InstRW<[SKXWriteResGroup7], (instregex "STAC")>;
@ -1283,48 +1275,35 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
let NumMicroOps = 1;
let ResourceCycles = [1];
}
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "ADD8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "AND8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CBW")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CLC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "CMP8rr")>;
def: InstRW<[SKXWriteResGroup10], (instrs CWDE)>;
def: InstRW<[SKXWriteResGroup10], (instregex "DEC(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "DEC8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "LAHF")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOV8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
def: InstRW<[SKXWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NEG(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NEG8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NEG(8|16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOOP")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT(16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT8r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "NOT(8|16|32|64)r")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "OR8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SAHF")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SIDT64m")>;
@ -1332,22 +1311,17 @@ def: InstRW<[SKXWriteResGroup10], (instregex "SLDT64m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SMSW16m")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STC")>;
def: InstRW<[SKXWriteResGroup10], (instregex "STRm")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SUB8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "SYSCALL")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "TEST8rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR(8|16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8i8")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8ri")>;
def: InstRW<[SKXWriteResGroup10], (instregex "XOR8rr")>;
def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
let Latency = 1;
@ -1552,14 +1526,10 @@ def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
let ResourceCycles = [2];
}
def: InstRW<[SKXWriteResGroup15], (instregex "CMOV(A|BE)(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL8r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL8ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR8r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR8ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup15], (instregex "ROR(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup15], (instregex "SET(A|BE)r")>;
def SKXWriteResGroup16 : SchedWriteRes<[SKXPort015]> {
@ -2122,16 +2092,11 @@ def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> {
let NumMicroOps = 3;
let ResourceCycles = [3];
}
def: InstRW<[SKXWriteResGroup35], (instregex "ROL(16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "ROL8rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "ROR(16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "ROR8rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SAR(16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SAR8rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHL(16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHL8rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHR(16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHR8rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "ROR(8|16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SAR(8|16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHL(8|16|32|64)rCL")>;
def: InstRW<[SKXWriteResGroup35], (instregex "SHR(8|16|32|64)rCL")>;
def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> {
let Latency = 3;
@ -2218,14 +2183,10 @@ def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
def: InstRW<[SKXWriteResGroup44], (instregex "RCL(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCL(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCL8r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCL8ri")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR(16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR(16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR8r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR8ri")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)ri")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR(8|16|32|64)r1")>;
def: InstRW<[SKXWriteResGroup44], (instregex "RCR(8|16|32|64)ri")>;
def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
let Latency = 3;
@ -2737,9 +2698,8 @@ def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
def: InstRW<[SKXWriteResGroup58], (instregex "MMX_MOVD64rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MMX_MOVD64to64rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MMX_MOVQ64rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOV(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOV(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOV64toPQIrm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOV8rm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOVDDUPrm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOVDI2PDIrm")>;
def: InstRW<[SKXWriteResGroup58], (instregex "MOVQI2PQIrm")>;
@ -2929,8 +2889,7 @@ def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
let NumMicroOps = 5;
let ResourceCycles = [2,3];
}
def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(16|32|64)rr")>;
def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG8rr")>;
def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>;
def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
let Latency = 5;
@ -3164,16 +3123,14 @@ def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup78], (instregex "ADC(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "ADC8rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "ADCX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "ADOX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup78], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "RORX(32|64)mi")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SARX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SBB(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SBB8rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SBB(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SHLX(32|64)rm")>;
def: InstRW<[SKXWriteResGroup78], (instregex "SHRX(32|64)rm")>;
@ -3202,27 +3159,18 @@ def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup81], (instregex "ADD(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "ADD8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "AND(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "AND8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP8mi")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP8mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "OR(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "OR8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "ADD(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "AND(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "CMP(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "OR(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "SUB(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "SUB8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "TEST(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "SUB(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "TEST(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "TEST8mi")>;
def: InstRW<[SKXWriteResGroup81], (instregex "TEST8mr")>;
def: InstRW<[SKXWriteResGroup81], (instregex "XOR(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "XOR8rm")>;
def: InstRW<[SKXWriteResGroup81], (instregex "XOR(8|16|32|64)rm")>;
def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
let Latency = 6;
@ -3276,54 +3224,34 @@ def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]
def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup86], (instregex "BTR(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup86], (instregex "BTS(16|32|64)mi8")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR8m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR8mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL8m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL8mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR8m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR8mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHL(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup86], (instregex "SHR(8|16|32|64)mi")>;
def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "DEC(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "DEC8m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "INC(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "INC8m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NEG(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NEG8m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NOT(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NOT8m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "ADD(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "AND(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "DEC(8|16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "INC(8|16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NEG(8|16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "NOT(8|16|32|64)m")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "OR(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm")>;
def: InstRW<[SKXWriteResGroup87], (instregex "PUSH(16|32|64)rmm")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR8mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "SUB(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup87], (instregex "XOR(8|16|32|64)mr")>;
def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
let Latency = 6;
@ -3905,22 +3833,17 @@ def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup107], (instregex "ROL(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROL(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROL8m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROL8mi")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR8m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR8mi")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup107], (instregex "ROR(8|16|32|64)mi")>;
def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 7;
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup108], (instregex "XADD(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup108], (instregex "XADD8rm")>;
def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 7;
@ -4545,58 +4468,44 @@ def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> {
let NumMicroOps = 5;
let ResourceCycles = [1,1,3];
}
def: InstRW<[SKXWriteResGroup126], (instregex "ROR(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup126], (instregex "ROR8mCL")>;
def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>;
def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCL8m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCL8mi")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR(16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR8m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR8mi")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR(8|16|32|64)m1")>;
def: InstRW<[SKXWriteResGroup127], (instregex "RCR(8|16|32|64)mi")>;
def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKXWriteResGroup128], (instregex "ROL(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "ROL8mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SAR(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SAR8mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHL(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHL8mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHR(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHR8mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SAR(8|16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHL(8|16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup128], (instregex "SHR(8|16|32|64)mCL")>;
def SKXWriteResGroup129 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,3];
}
def: InstRW<[SKXWriteResGroup129], (instregex "ADC(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup129], (instregex "ADC8mi")>;
def: InstRW<[SKXWriteResGroup129], (instregex "ADC(8|16|32|64)mi")>;
def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 8;
let NumMicroOps = 6;
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKXWriteResGroup130], (instregex "ADC(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "ADC8mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG8rm")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB(16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mi")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB8mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mr")>;
def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB(8|16|32|64)mi")>;
def: InstRW<[SKXWriteResGroup130], (instregex "SBB(8|16|32|64)mr")>;
def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
@ -5233,8 +5142,7 @@ def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,
let NumMicroOps = 8;
let ResourceCycles = [1,1,1,1,1,3];
}
def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(16|32|64)rm")>;
def: InstRW<[SKXWriteResGroup157], (instregex "XCHG8rm")>;
def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
def SKXWriteResGroup158 : SchedWriteRes<[SKXPort05,SKXPort0156]> {
let Latency = 10;
@ -5772,8 +5680,7 @@ def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06
let NumMicroOps = 10;
let ResourceCycles = [1,1,1,5,1,1];
}
def: InstRW<[SKXWriteResGroup195], (instregex "RCL(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup195], (instregex "RCL8mCL")>;
def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
def SKXWriteResGroup196 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 16;
@ -5890,8 +5797,7 @@ def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06
let NumMicroOps = 11;
let ResourceCycles = [2,1,1,4,1,2];
}
def: InstRW<[SKXWriteResGroup208], (instregex "RCR(16|32|64)mCL")>;
def: InstRW<[SKXWriteResGroup208], (instregex "RCR8mCL")>;
def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23]> {
let Latency = 19;
@ -6207,8 +6113,7 @@ def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156
let NumMicroOps = 8;
let ResourceCycles = [2,4,1,1];
}
def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(16|32|64)m")>;
def: InstRW<[SKXWriteResGroup241], (instregex "IDIV8m")>;
def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>;
def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
let Latency = 29;
@ -6252,20 +6157,16 @@ def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,S
let NumMicroOps = 23;
let ResourceCycles = [1,5,3,4,10];
}
def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)ri")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN(16|32)rr")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN8ri")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN8rr")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri")>;
def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)rr")>;
def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
let Latency = 35;
let NumMicroOps = 23;
let ResourceCycles = [1,5,2,1,4,10];
}
def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)ir")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT(16|32)rr")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT8ir")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT8rr")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir")>;
def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)rr")>;
def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
let Latency = 37;