forked from OSchip/llvm-project
Switch loads over to use memri as the operand instead of a reg/imm operand
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented out patterns. More improvement is needed to enable the patterns, but we're getting close. llvm-svn: 31749
This commit is contained in:
Chris Lattner
parent
c94f214d22
commit
1396961e85
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@ -234,14 +234,14 @@ void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
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unsigned ThisStoreSize;
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switch (Opcode) {
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default: assert(0 && "Unknown store instruction!");
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case PPC::STB:
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case PPC::STB: case PPC::STBU:
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case PPC::STBX:
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case PPC::STB8:
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case PPC::STBX8:
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case PPC::STVEBX:
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ThisStoreSize = 1;
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break;
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case PPC::STH:
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case PPC::STH: case PPC::STHU:
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case PPC::STHX:
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case PPC::STH8:
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case PPC::STHX8:
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@ -249,12 +249,11 @@ void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
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case PPC::STHBRX:
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ThisStoreSize = 2;
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break;
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case PPC::STFS:
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case PPC::STFS: case PPC::STFSU:
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case PPC::STFSX:
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case PPC::STWU:
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case PPC::STWX:
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case PPC::STWUX:
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case PPC::STW:
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case PPC::STW: case PPC::STWU:
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case PPC::STW8:
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case PPC::STWX8:
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case PPC::STVEWX:
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@ -264,7 +263,7 @@ void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
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break;
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case PPC::STD_32:
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case PPC::STDX_32:
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case PPC::STD:
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case PPC::STD: case PPC::STDU:
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case PPC::STFD:
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case PPC::STFDX:
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case PPC::STDX:
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@ -247,7 +247,7 @@ def crbitm: Operand<i8> {
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// Address operands
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let MIOperandInfo = (ops i32imm, ptr_rc);
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let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
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}
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def memrr : Operand<iPTR> {
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let PrintMethod = "printMemRegReg";
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@ -270,6 +270,7 @@ def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
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def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
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def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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def FPContractions : Predicate<"!NoExcessFPPrecision">;
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@ -410,7 +411,7 @@ def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
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// PPC32 Load Instructions.
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//
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// Unindexed (r+i) Loads.
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// Unindexed (r+i) Loads.
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let isLoad = 1, PPC970_Unit = 2 in {
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def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
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"lbz $rD, $src", LdStGeneral,
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@ -434,38 +435,32 @@ def LFD : DForm_1<50, (ops F8RC:$rD, memri:$src),
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[(set F8RC:$rD, (load iaddr:$src))]>;
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// 'Update' load forms.
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def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lbzu $rD, $disp($rA)", LdStGeneral,
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[]>, RegConstraint<"$rA = $rA_result">;
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// Unindexed (r+i) Loads with Update (preinc).
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def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lbzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lhau $rD, $disp($rA)", LdStGeneral,
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[]>, RegConstraint<"$rA = $rA_result">;
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def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lhau $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lhzu $rD, $disp($rA)", LdStGeneral,
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[]>, RegConstraint<"$rA = $rA_result">;
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def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lhzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lwzu $rD, $disp($rA)", LdStGeneral,
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[]>, RegConstraint<"$rA = $rA_result">;
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def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lwzu $rD, $addr", LdStGeneral,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lfs $rD, $disp($rA)", LdStLFDU,
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[]>, RegConstraint<"$rA = $rA_result">;
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def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
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ptr_rc:$rA),
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"lfd $rD, $disp($rA)", LdStLFD,
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[]>, RegConstraint<"$rA = $rA_result">;
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def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lfs $rD, $addr", LdStLFDU,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
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"lfd $rD, $addr", LdStLFD,
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[]>, RegConstraint<"$addr.reg = $ea_result">;
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}
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// Indexed (r+r) loads.
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// Indexed (r+r) Loads.
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//
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let isLoad = 1, PPC970_Unit = 2 in {
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def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
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@ -502,7 +497,7 @@ def LFDX : XForm_25<31, 599, (ops F8RC:$frD, memrr:$src),
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// PPC32 Store Instructions.
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//
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// Unindexed (r+i) Stores.
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// Unindexed (r+i) Stores.
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
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"stb $rS, $src", LdStGeneral,
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@ -513,10 +508,6 @@ def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
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def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
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"stw $rS, $src", LdStGeneral,
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[(store GPRC:$rS, iaddr:$src)]>;
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def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
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"stwu $rS, $disp($rA)", LdStGeneral,
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[]>;
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def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
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"stfs $rS, $dst", LdStUX,
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[(store F4RC:$rS, iaddr:$dst)]>;
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@ -525,6 +516,33 @@ def STFD : DForm_1<54, (ops F8RC:$rS, memri:$dst),
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[(store F8RC:$rS, iaddr:$dst)]>;
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}
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// Unindexed (r+i) Stores with Update (preinc).
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let isStore = 1, PPC970_Unit = 2 in {
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def STBU : DForm_3<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"stbu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res,
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(pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STHU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"sthu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res,
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(pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STWU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
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"stwu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STFSU : DForm_3<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
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"stfsu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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def STFDU : DForm_3<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
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"stfdu $rS, $addr", LdStGeneral,
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[/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>,
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RegConstraint<"$addr.reg = $ea_res">;
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}
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// Indexed (r+r) Stores.
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//
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let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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