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Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance. 

Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

llvm-svn: 123107
This commit is contained in:
Jakob Stoklund Olesen 2011-01-09 03:05:53 +00:00
parent 7f93d8d62c
commit 1331a15b0c
15 changed files with 81 additions and 110 deletions
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30
llvm/include/llvm/Target/TargetRegisterInfo.h
View File

@ -333,9 +333,6 @@ public:
return Index + FirstVirtualRegister;
}
/// printReg - Print a virtual or physical register on OS.
void printReg(unsigned Reg, raw_ostream &OS) const;
/// getMinimalPhysRegClass - Returns the Register Class of a physical
/// register of the given type, picking the most sub register class of
/// the right type that contains this physreg.
@ -758,6 +755,33 @@ struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B);
/// PrintReg - Helper class for printing registers on a raw_ostream.
/// Prints virtual and physical registers with or without a TRI instance.
///
/// The format is:
/// %noreg - NoRegister
/// %reg5 - a virtual register.
/// %reg5:sub_8bit - a virtual register with sub-register index (with TRI).
/// %EAX - a physical register
/// %physreg17 - a physical register when no TRI instance given.
///
/// Usage: OS << PrintReg(Reg, TRI) << '\n';
///
class PrintReg {
const TargetRegisterInfo *TRI;
unsigned Reg;
unsigned SubIdx;
public:
PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
: TRI(tri), Reg(reg), SubIdx(subidx) {}
void print(raw_ostream&) const;
};
static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
PR.print(OS);
return OS;
}
} // End llvm namespace
#endif

4
llvm/lib/CodeGen/CalcSpillWeights.cpp
View File

@ -222,7 +222,7 @@ void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
if (rc == orc)
return;
DEBUG(dbgs() << "Inflating " << orc->getName() << ":%reg" << reg << " to "
<< rc->getName() <<".\n");
DEBUG(dbgs() << "Inflating " << orc->getName() << ':' << PrintReg(reg)
<< " to " << rc->getName() <<".\n");
mri.setRegClass(reg, rc);
}

7
llvm/lib/CodeGen/LiveDebugVariables.cpp
View File

@ -374,12 +374,7 @@ void Location::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
return;
default:
if (isReg()) {
if (TargetRegisterInfo::isVirtualRegister(Kind)) {
OS << "%reg" << Kind;
if (Data.SubIdx)
OS << ':' << TRI->getSubRegIndexName(Data.SubIdx);
} else
OS << '%' << TRI->getName(Kind);
OS << PrintReg(Kind, TRI, Data.SubIdx);
} else {
OS << "fi#" << ~Kind;
if (Data.Offset)

4
llvm/lib/CodeGen/LiveInterval.cpp
View File

@ -652,10 +652,8 @@ void LiveRange::dump() const {
void LiveInterval::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
if (isStackSlot())
OS << "SS#" << getStackSlotIndex();
else if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
OS << TRI->getName(reg);
else
OS << "%reg" << reg;
OS << PrintReg(reg, TRI);
OS << ',' << weight;

24
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -245,15 +245,6 @@ bool LiveIntervals::conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
return false;
}
#ifndef NDEBUG
static void printRegName(unsigned reg, const TargetRegisterInfo* tri_) {
if (TargetRegisterInfo::isPhysicalRegister(reg))
dbgs() << tri_->getName(reg);
else
dbgs() << "%reg" << reg;
}
#endif
static
bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
unsigned Reg = MI.getOperand(MOIdx).getReg();
@ -295,10 +286,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
MachineOperand& MO,
unsigned MOIdx,
LiveInterval &interval) {
DEBUG({
dbgs() << "\t\tregister: ";
printRegName(interval.reg, tri_);
});
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
// Virtual registers may be defined multiple times (due to phi
// elimination and 2-addr elimination). Much of what we do only has to be
@ -498,10 +486,7 @@ void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
MachineInstr *CopyMI) {
// A physical register cannot be live across basic block, so its
// lifetime must end somewhere in its defining basic block.
DEBUG({
dbgs() << "\t\tregister: ";
printRegName(interval.reg, tri_);
});
DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
SlotIndex baseIndex = MIIdx;
SlotIndex start = baseIndex.getDefIndex();
@ -605,10 +590,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
SlotIndex MIIdx,
LiveInterval &interval, bool isAlias) {
DEBUG({
dbgs() << "\t\tlivein register: ";
printRegName(interval.reg, tri_);
});
DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
// Look for kills, if it reaches a def before it's killed, then it shouldn't
// be considered a livein.

11
llvm/lib/CodeGen/LiveIntervalUnion.cpp
View File

@ -69,23 +69,22 @@ void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
void
LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
OS << "LIU ";
TRI->printReg(RepReg, OS);
OS << "LIU " << PrintReg(RepReg, TRI);
if (empty()) {
OS << " empty\n";
return;
}
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
OS << " [" << SI.start() << ' ' << SI.stop() << "):";
TRI->printReg(SI.value()->reg, OS);
OS << " [" << SI.start() << ' ' << SI.stop() << "):"
<< PrintReg(SI.value()->reg, TRI);
}
OS << '\n';
}
void LiveIntervalUnion::InterferenceResult::print(raw_ostream &OS,
const TargetRegisterInfo *TRI) const {
OS << '[' << start() << ';' << stop() << "):";
TRI->printReg(interference()->reg, OS);
OS << '[' << start() << ';' << stop() << "):"
<< PrintReg(interference()->reg, TRI);
}
void LiveIntervalUnion::Query::print(raw_ostream &OS,

13
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -166,17 +166,6 @@ void MachineBasicBlock::dump() const {
print(dbgs());
}
static inline void OutputReg(raw_ostream &os, unsigned RegNo,
const TargetRegisterInfo *TRI = 0) {
if (RegNo != 0 && TargetRegisterInfo::isPhysicalRegister(RegNo)) {
if (TRI)
os << " %" << TRI->get(RegNo).Name;
else
os << " %physreg" << RegNo;
} else
os << " %reg" << RegNo;
}
StringRef MachineBasicBlock::getName() const {
if (const BasicBlock *LBB = getBasicBlock())
return LBB->getName();
@ -214,7 +203,7 @@ void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
if (Indexes) OS << '\t';
OS << " Live Ins:";
for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
OutputReg(OS, *I, TRI);
OS << PrintReg(*I, TRI);
OS << '\n';
}
// Print the preds of this block according to the CFG.

21
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -227,24 +227,11 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
if (const MachineBasicBlock *MBB = MI->getParent())
if (const MachineFunction *MF = MBB->getParent())
TM = &MF->getTarget();
const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
switch (getType()) {
case MachineOperand::MO_Register:
if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
OS << "%reg" << getReg();
} else {
if (TM)
OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
else
OS << "%physreg" << getReg();
}
if (getSubReg() != 0) {
if (TM)
OS << ':' << TM->getRegisterInfo()->getSubRegIndexName(getSubReg());
else
OS << ':' << getSubReg();
}
OS << PrintReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isEarlyClobber()) {
@ -1448,14 +1435,14 @@ void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
if (!HaveSemi) OS << ";"; HaveSemi = true;
for (unsigned i = 0; i != VirtRegs.size(); ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClass(VirtRegs[j]) != RC) {
++j;
continue;
}
if (VirtRegs[i] != VirtRegs[j])
OS << "," << VirtRegs[j];
OS << "," << PrintReg(VirtRegs[j]);
VirtRegs.erase(VirtRegs.begin()+j);
}
}

4
llvm/lib/CodeGen/MachineVerifier.cpp
View File

@ -936,13 +936,13 @@ void MachineVerifier::verifyLiveVariables() {
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MFI->getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", MFI);
*OS << "Virtual register %reg" << Reg
*OS << "Virtual register " << PrintReg(Reg)
<< " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MFI->getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", MFI);
*OS << "Virtual register %reg" << Reg
*OS << "Virtual register " << PrintReg(Reg)
<< " is not needed live through the block.\n";
}
}

2
llvm/lib/CodeGen/PHIElimination.cpp
View File

@ -211,7 +211,7 @@ void PHIElimination::LowerAtomicPHINode(
IncomingReg = entry;
reusedIncoming = true;
++NumReused;
DEBUG(dbgs() << "Reusing %reg" << IncomingReg << " for " << *MPhi);
DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
} else {
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);

20
llvm/lib/CodeGen/RegAllocFast.cpp
View File

@ -262,8 +262,8 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
// instruction, not on the spill.
bool SpillKill = LR.LastUse != MI;
LR.Dirty = false;
DEBUG(dbgs() << "Spilling %reg" << LRI->first
<< " in " << TRI->getName(LR.PhysReg));
DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI)
<< " in " << PrintReg(LR.PhysReg, TRI));
const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
int FI = getStackSpaceFor(LRI->first, RC);
DEBUG(dbgs() << " to stack slot #" << FI << "\n");
@ -461,8 +461,8 @@ unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
/// register must not be used for anything else when this is called.
///
void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
<< TRI->getName(PhysReg) << "\n");
DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to "
<< PrintReg(PhysReg, TRI) << "\n");
PhysRegState[PhysReg] = LRE.first;
assert(!LRE.second.PhysReg && "Already assigned a physreg");
LRE.second.PhysReg = PhysReg;
@ -506,8 +506,8 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
return assignVirtToPhysReg(LRE, PhysReg);
}
DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
<< "\n");
DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
<< RC->getName() << "\n");
unsigned BestReg = 0, BestCost = spillImpossible;
for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
@ -587,8 +587,8 @@ RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
allocVirtReg(MI, *LRI, Hint);
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
<< TRI->getName(LR.PhysReg) << "\n");
DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
<< PrintReg(LR.PhysReg, TRI) << "\n");
TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
++NumLoads;
} else if (LR.Dirty) {
@ -660,7 +660,7 @@ void RAFast::handleThroughOperands(MachineInstr *MI,
if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
(MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
if (ThroughRegs.insert(Reg))
DEBUG(dbgs() << " %reg" << Reg);
DEBUG(dbgs() << ' ' << PrintReg(Reg));
}
}
@ -764,7 +764,7 @@ void RAFast::AllocateBasicBlock() {
dbgs() << "*";
break;
default:
dbgs() << "=%reg" << PhysRegState[Reg];
dbgs() << '=' << PrintReg(PhysRegState[Reg]);
if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
dbgs() << "*";
assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&

7
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -6021,12 +6021,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
OS << LBB->getName() << " ";
OS << (const void*)BBDN->getBasicBlock() << ">";
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
if (G && R->getReg() &&
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
OS << " %" << G->getTarget().getRegisterInfo()->getName(R->getReg());
} else {
OS << " %reg" << R->getReg();
}
OS << ' ' << PrintReg(R->getReg(), G ? G->getTarget().getRegisterInfo() :0);
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(this)) {
OS << "'" << ES->getSymbol() << "'";

12
llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -985,23 +985,19 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
return false;
}
DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_));
// Enforce policies.
if (CP.isPhys()) {
DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
DEBUG(dbgs() <<" with physreg " << PrintReg(CP.getDstReg(), tri_) << "\n");
// Only coalesce to allocatable physreg.
if (!li_->isAllocatable(CP.getDstReg())) {
DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
return false; // Not coalescable.
}
} else {
DEBUG({
dbgs() << " with reg%" << CP.getDstReg();
if (CP.getSubIdx())
dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
dbgs() << " to " << CP.getNewRC()->getName() << "\n";
});
DEBUG(dbgs() << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx())
<< " to " << CP.getNewRC()->getName() << "\n");
// Avoid constraining virtual register regclass too much.
if (CP.isCrossClass()) {

12
llvm/lib/CodeGen/VirtRegMap.cpp
View File

@ -263,20 +263,16 @@ void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
OS << '[';
TRI->printReg(Reg, OS);
OS << " -> ";
TRI->printReg(Virt2PhysMap[Reg], OS);
OS << "] " << MRI.getRegClass(i)->getName() << "\n";
OS << '[' << PrintReg(Reg, TRI) << " -> "
<< PrintReg(Virt2PhysMap[Reg], TRI) << "] "
<< MRI.getRegClass(Reg)->getName() << "\n";
}
}
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
OS << '[';
TRI->printReg(Reg, OS);
OS << " -> fi#" << Virt2StackSlotMap[Reg]
OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
<< "] " << MRI.getRegClass(Reg)->getName() << "\n";
}
}

20
llvm/lib/Target/TargetRegisterInfo.cpp
View File

@ -31,7 +31,7 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
AliasesHash(aliases), AliasesHashSize(aliasessize),
Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
RegClassBegin(RCB), RegClassEnd(RCE) {
assert(NumRegs < FirstVirtualRegister &&
assert(isPhysicalRegister(NumRegs) &&
"Target has too many physical registers!");
CallFrameSetupOpcode = CFSO;
@ -40,11 +40,21 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
TargetRegisterInfo::~TargetRegisterInfo() {}
void TargetRegisterInfo::printReg(unsigned Reg, raw_ostream &OS) const {
if (Reg && isVirtualRegister(Reg))
OS << "%reg" << Reg;
void PrintReg::print(raw_ostream &OS) const {
if (!Reg)
OS << "%noreg";
else if (TargetRegisterInfo::isVirtualRegister(Reg))
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
else if (TRI)
OS << '%' << TRI->getName(Reg);
else
OS << '%' << getName(Reg);
OS << "%physreg" << Reg;
if (SubIdx) {
if (TRI)
OS << ':' << TRI->getSubRegIndexName(SubIdx);
else
OS << ":sub(" << SubIdx << ')';
}
}
/// getMinimalPhysRegClass - Returns the Register Class of a physical