maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[PowerPC] Fix issue with strict float to int conversion. 

When doing the float to int conversion the strict conversion also needs to
retun a chain. This patch fixes that.

Reviewed By: nemanjai, #powerpc, qiucf

Differential Revision: https://reviews.llvm.org/D117464
This commit is contained in:
Stefan Pintilie 2022-01-19 09:33:18 -06:00
parent cc639dde8c
commit 1324bb29f7
2 changed files with 60 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -11178,13 +11178,17 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::FP_TO_UINT: {
// LowerFP_TO_INT() can only handle f32 and f64.
if (N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType() ==
MVT::ppcf128)
return;
Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
SDValue LoweredValue = LowerFP_TO_INT(SDValue(N, 0), DAG, dl);
Results.push_back(LoweredValue);
if (N->isStrictFPOpcode())
Results.push_back(LoweredValue.getValue(1));
return;
}
case ISD::TRUNCATE: {
if (!N->getValueType(0).isVector())
return;

54
llvm/test/CodeGen/PowerPC/aix-fptoint.ll Normal file
View File

@ -0,0 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -mtriple powerpc-ibm-aix -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
; RUN: llc -O3 -mtriple powerpc64-ibm-aix -verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
; Function Attrs: nounwind strictfp
define i64 @tester_s(double %d) local_unnamed_addr #0 {
; 32BIT-LABEL: tester_s:
; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: xscvdpsxds 0, 1
; 32BIT-NEXT: stfd 0, -8(1)
; 32BIT-NEXT: lwz 3, -8(1)
; 32BIT-NEXT: lwz 4, -4(1)
; 32BIT-NEXT: blr
;
; 64BIT-LABEL: tester_s:
; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: xscvdpsxds 0, 1
; 64BIT-NEXT: stfd 0, -8(1)
; 64BIT-NEXT: ld 3, -8(1)
; 64BIT-NEXT: blr
entry:
%conv = tail call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %d, metadata !"fpexcept.ignore") #2
ret i64 %conv
}
; Function Attrs: nounwind strictfp
define i64 @tester_u(double %d) local_unnamed_addr #0 {
; 32BIT-LABEL: tester_u:
; 32BIT: # %bb.0: # %entry
; 32BIT-NEXT: xscvdpuxds 0, 1
; 32BIT-NEXT: stfd 0, -8(1)
; 32BIT-NEXT: lwz 3, -8(1)
; 32BIT-NEXT: lwz 4, -4(1)
; 32BIT-NEXT: blr
;
; 64BIT-LABEL: tester_u:
; 64BIT: # %bb.0: # %entry
; 64BIT-NEXT: xscvdpuxds 0, 1
; 64BIT-NEXT: stfd 0, -8(1)
; 64BIT-NEXT: ld 3, -8(1)
; 64BIT-NEXT: blr
entry:
%conv = tail call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %d, metadata !"fpexcept.ignore") #2
ret i64 %conv
}
; Function Attrs: nounwind
declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata) #1
declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata) #1
attributes #0 = { nounwind strictfp "strictfp" "target-cpu"="pwr7" }
attributes #1 = { nounwind }