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Fix incorrect atomics codegen introduced in r154705, and extend test to catch it. 

llvm-svn: 154845
This commit is contained in:
Richard Smith 2012-04-16 18:43:53 +00:00
parent 433e05306f
commit 12da79b859
2 changed files with 9 additions and 4 deletions
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2
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -11420,7 +11420,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
t3 = t2;
MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
MIB.addReg(t3);
MIB.addReg(t1);
MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
for (int i=0; i <= lastAddrIndx; ++i)

11
llvm/test/CodeGen/X86/atomic_op.ll
View File

@ -107,10 +107,15 @@ entry:
; CHECK: cmpxchgl
%17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
store i32 %17, i32* %old
; CHECK: andl
; CHECK: notl
; CHECK: movl $1401, %[[R17mask:[a-z]*]]
; CHECK: movl [[R17atomic:.*]], %eax
; CHECK: movl %eax, %[[R17newval:[a-z]*]]
; CHECK: andl %[[R17mask]], %[[R17newval]]
; CHECK: notl %[[R17newval]]
; CHECK: lock
; CHECK: cmpxchgl
; CHECK: cmpxchgl %[[R17newval]], [[R17atomic]]
; CHECK: jne
; CHECK: movl %eax,
%18 = atomicrmw nand i32* %val2, i32 1401 monotonic
store i32 %18, i32* %old
; CHECK: andl