forked from OSchip/llvm-project
parent
3fe975b846
commit
12c6d89204
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@ -35,8 +35,8 @@ namespace {
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Statistic<> NumNoops ("scheduler", "Number of noops inserted");
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Statistic<> NumNoops ("scheduler", "Number of noops inserted");
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Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
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Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or a
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/// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
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/// group of nodes flagged together.
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/// a group of nodes flagged together.
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struct SUnit {
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struct SUnit {
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SDNode *Node; // Representative node.
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SDNode *Node; // Representative node.
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std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
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std::vector<SDNode*> FlaggedNodes; // All nodes flagged to Node.
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@ -44,14 +44,14 @@ namespace {
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std::set<SUnit*> ChainPreds; // All chain predecessors.
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std::set<SUnit*> ChainPreds; // All chain predecessors.
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std::set<SUnit*> Succs; // All real successors.
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std::set<SUnit*> Succs; // All real successors.
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std::set<SUnit*> ChainSuccs; // All chain successors.
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std::set<SUnit*> ChainSuccs; // All chain successors.
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int NumPredsLeft; // # of preds not scheduled.
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short NumPredsLeft; // # of preds not scheduled.
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int NumSuccsLeft; // # of succs not scheduled.
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short NumSuccsLeft; // # of succs not scheduled.
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int NumChainPredsLeft; // # of chain preds not scheduled.
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short NumChainPredsLeft; // # of chain preds not scheduled.
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int NumChainSuccsLeft; // # of chain succs not scheduled.
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short NumChainSuccsLeft; // # of chain succs not scheduled.
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int SethiUllman; // Sethi Ullman number.
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int SethiUllman; // Sethi Ullman number.
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bool isTwoAddress; // Is a two-address instruction.
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bool isTwoAddress : 1; // Is a two-address instruction.
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bool isDefNUseOperand; // Is a def&use operand.
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bool isDefNUseOperand : 1; // Is a def&use operand.
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unsigned Latency; // Node latency.
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unsigned short Latency; // Node latency.
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unsigned CycleBound; // Upper/lower cycle to be scheduled at.
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unsigned CycleBound; // Upper/lower cycle to be scheduled at.
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SUnit *Next;
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SUnit *Next;
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@ -247,7 +247,7 @@ void ScheduleDAGList::ReleasePred(AvailableQueueTy &Available,
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// latency. For example, the reader can very well read the register written
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurrCycle + PredSU->Latency);
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PredSU->CycleBound = std::max(PredSU->CycleBound,CurrCycle + PredSU->Latency);
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if (!isChain)
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if (!isChain)
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PredSU->NumSuccsLeft--;
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PredSU->NumSuccsLeft--;
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@ -278,7 +278,7 @@ void ScheduleDAGList::ReleaseSucc(AvailableQueueTy &Available,
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// latency. For example, the reader can very well read the register written
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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// interrupt model (drain vs. freeze).
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SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurrCycle + SuccSU->Latency);
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SuccSU->CycleBound = std::max(SuccSU->CycleBound,CurrCycle + SuccSU->Latency);
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if (!isChain)
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if (!isChain)
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SuccSU->NumPredsLeft--;
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SuccSU->NumPredsLeft--;
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