forked from OSchip/llvm-project
Update for LLVM changes
InstSimplify has gained the ability to remove needless bitcasts which perturbed some clang codegen tests. llvm-svn: 276728
This commit is contained in:
David Majnemer
parent
a90a621d1e
commit
12b9e76b62
File diff suppressed because it is too large
Load Diff
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@ -14,9 +14,7 @@ int16_t test_vaddlv_s8(int8x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vaddlv_s16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: ret i32 [[VADDLV_I]]
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int32_t test_vaddlv_s16(int16x4_t a) {
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return vaddlv_s16(a);
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@ -31,9 +29,7 @@ uint16_t test_vaddlv_u8(uint8x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vaddlv_u16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: ret i32 [[VADDLV_I]]
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uint32_t test_vaddlv_u16(uint16x4_t a) {
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return vaddlv_u16(a);
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@ -48,18 +44,14 @@ int16_t test_vaddlvq_s8(int8x16_t a) {
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}
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// CHECK-LABEL: define i32 @test_vaddlvq_s16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: ret i32 [[VADDLV_I]]
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int32_t test_vaddlvq_s16(int16x8_t a) {
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return vaddlvq_s16(a);
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}
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// CHECK-LABEL: define i64 @test_vaddlvq_s32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %a) #2
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// CHECK: ret i64 [[VADDLVQ_S32_I]]
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int64_t test_vaddlvq_s32(int32x4_t a) {
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return vaddlvq_s32(a);
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@ -74,18 +66,14 @@ uint16_t test_vaddlvq_u8(uint8x16_t a) {
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}
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// CHECK-LABEL: define i32 @test_vaddlvq_u16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: ret i32 [[VADDLV_I]]
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uint32_t test_vaddlvq_u16(uint16x8_t a) {
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return vaddlvq_u16(a);
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}
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// CHECK-LABEL: define i64 @test_vaddlvq_u32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> %a) #2
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// CHECK: ret i64 [[VADDLVQ_U32_I]]
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uint64_t test_vaddlvq_u32(uint32x4_t a) {
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return vaddlvq_u32(a);
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@ -100,9 +88,7 @@ int8_t test_vmaxv_s8(int8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vmaxv_s16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vmaxv_s16(int16x4_t a) {
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@ -118,9 +104,7 @@ uint8_t test_vmaxv_u8(uint8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vmaxv_u16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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uint16_t test_vmaxv_u16(uint16x4_t a) {
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@ -136,9 +120,7 @@ int8_t test_vmaxvq_s8(int8x16_t a) {
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}
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// CHECK-LABEL: define i16 @test_vmaxvq_s16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vmaxvq_s16(int16x8_t a) {
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@ -146,9 +128,7 @@ int16_t test_vmaxvq_s16(int16x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vmaxvq_s32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a) #2
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// CHECK: ret i32 [[VMAXVQ_S32_I]]
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int32_t test_vmaxvq_s32(int32x4_t a) {
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return vmaxvq_s32(a);
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@ -163,9 +143,7 @@ uint8_t test_vmaxvq_u8(uint8x16_t a) {
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}
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// CHECK-LABEL: define i16 @test_vmaxvq_u16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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uint16_t test_vmaxvq_u16(uint16x8_t a) {
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@ -173,9 +151,7 @@ uint16_t test_vmaxvq_u16(uint16x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vmaxvq_u32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a) #2
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// CHECK: ret i32 [[VMAXVQ_U32_I]]
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uint32_t test_vmaxvq_u32(uint32x4_t a) {
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return vmaxvq_u32(a);
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@ -190,9 +166,7 @@ int8_t test_vminv_s8(int8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vminv_s16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vminv_s16(int16x4_t a) {
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@ -208,9 +182,7 @@ uint8_t test_vminv_u8(uint8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vminv_u16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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uint16_t test_vminv_u16(uint16x4_t a) {
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@ -226,9 +198,7 @@ int8_t test_vminvq_s8(int8x16_t a) {
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}
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// CHECK-LABEL: define i16 @test_vminvq_s16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vminvq_s16(int16x8_t a) {
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@ -236,9 +206,7 @@ int16_t test_vminvq_s16(int16x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vminvq_s32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a) #2
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// CHECK: ret i32 [[VMINVQ_S32_I]]
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int32_t test_vminvq_s32(int32x4_t a) {
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return vminvq_s32(a);
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@ -253,9 +221,7 @@ uint8_t test_vminvq_u8(uint8x16_t a) {
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}
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// CHECK-LABEL: define i16 @test_vminvq_u16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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uint16_t test_vminvq_u16(uint16x8_t a) {
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@ -263,9 +229,7 @@ uint16_t test_vminvq_u16(uint16x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vminvq_u32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
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// CHECK: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> [[TMP1]]) #2
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// CHECK: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a) #2
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// CHECK: ret i32 [[VMINVQ_U32_I]]
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uint32_t test_vminvq_u32(uint32x4_t a) {
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return vminvq_u32(a);
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@ -280,9 +244,7 @@ int8_t test_vaddv_s8(int8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vaddv_s16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vaddv_s16(int16x4_t a) {
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@ -298,9 +260,7 @@ uint8_t test_vaddv_u8(uint8x8_t a) {
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}
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// CHECK-LABEL: define i16 @test_vaddv_u16(<4 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> [[TMP1]]) #2
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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uint16_t test_vaddv_u16(uint16x4_t a) {
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@ -316,9 +276,7 @@ int8_t test_vaddvq_s8(int8x16_t a) {
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}
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// CHECK-LABEL: define i16 @test_vaddvq_s16(<8 x i16> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
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// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> [[TMP1]]) #2
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// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a) #2
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// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
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// CHECK: ret i16 [[TMP2]]
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int16_t test_vaddvq_s16(int16x8_t a) {
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@ -326,9 +284,7 @@ int16_t test_vaddvq_s16(int16x8_t a) {
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}
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// CHECK-LABEL: define i32 @test_vaddvq_s32(<4 x i32> %a) #0 {
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// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
|
||||
// CHECK: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> [[TMP1]]) #2
|
||||
// CHECK: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a) #2
|
||||
// CHECK: ret i32 [[VADDVQ_S32_I]]
|
||||
int32_t test_vaddvq_s32(int32x4_t a) {
|
||||
return vaddvq_s32(a);
|
||||
|
|
@ -343,9 +299,7 @@ uint8_t test_vaddvq_u8(uint8x16_t a) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define i16 @test_vaddvq_u16(<8 x i16> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
|
||||
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> [[TMP1]]) #2
|
||||
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a) #2
|
||||
// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
|
||||
// CHECK: ret i16 [[TMP2]]
|
||||
uint16_t test_vaddvq_u16(uint16x8_t a) {
|
||||
|
|
@ -353,45 +307,35 @@ uint16_t test_vaddvq_u16(uint16x8_t a) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define i32 @test_vaddvq_u32(<4 x i32> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
|
||||
// CHECK: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> [[TMP1]]) #2
|
||||
// CHECK: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a) #2
|
||||
// CHECK: ret i32 [[VADDVQ_U32_I]]
|
||||
uint32_t test_vaddvq_u32(uint32x4_t a) {
|
||||
return vaddvq_u32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define float @test_vmaxvq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[TMP1]]) #2
|
||||
// CHECK: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret float [[VMAXVQ_F32_I]]
|
||||
float32_t test_vmaxvq_f32(float32x4_t a) {
|
||||
return vmaxvq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define float @test_vminvq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> [[TMP1]]) #2
|
||||
// CHECK: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret float [[VMINVQ_F32_I]]
|
||||
float32_t test_vminvq_f32(float32x4_t a) {
|
||||
return vminvq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define float @test_vmaxnmvq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[TMP1]]) #2
|
||||
// CHECK: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret float [[VMAXNMVQ_F32_I]]
|
||||
float32_t test_vmaxnmvq_f32(float32x4_t a) {
|
||||
return vmaxnmvq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define float @test_vminnmvq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> [[TMP1]]) #2
|
||||
// CHECK: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret float [[VMINNMVQ_F32_I]]
|
||||
float32_t test_vminnmvq_f32(float32x4_t a) {
|
||||
return vminnmvq_f32(a);
|
||||
|
|
|
|||
|
|
@ -214,13 +214,7 @@ float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
|
|||
// CHECK-LABEL: define <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #0 {
|
||||
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
|
||||
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
|
||||
// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
|
||||
// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]], <2 x double> [[TMP3]]) #2
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> [[VECINIT1_I]], <2 x double> %a)
|
||||
// CHECK: ret <2 x double> [[TMP6]]
|
||||
float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
|
||||
return vfmaq_n_f64(a, b, c);
|
||||
|
|
@ -230,13 +224,7 @@ float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
|
|||
// CHECK: [[SUB_I:%.*]] = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %b
|
||||
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
|
||||
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x double> [[SUB_I]] to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
|
||||
// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x double>
|
||||
// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x double>
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]], <2 x double> [[TMP3]]) #2
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[SUB_I]], <2 x double> [[VECINIT1_I]], <2 x double> %a) #2
|
||||
// CHECK: ret <2 x double> [[TMP6]]
|
||||
float64x2_t test_vfmsq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
|
||||
return vfmsq_n_f64(a, b, c);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -47,9 +47,7 @@ float64_t test_vmuld_laneq_f64(float64_t a, float64x2_t b) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define <1 x double> @test_vmul_n_f64(<1 x double> %a, double %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <1 x double> [[TMP1]] to double
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %a to double
|
||||
// CHECK: [[TMP3:%.*]] = fmul double [[TMP2]], %b
|
||||
// CHECK: [[TMP4:%.*]] = bitcast double [[TMP3]] to <1 x double>
|
||||
// CHECK: ret <1 x double> [[TMP4]]
|
||||
|
|
|
|||
|
|
@ -23,11 +23,7 @@ uint64x2_t test_vceqq_p64(poly64x2_t a, poly64x2_t b) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define <1 x i64> @test_vtst_p64(<1 x i64> %a, <1 x i64> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
|
||||
// CHECK: [[TMP4:%.*]] = and <1 x i64> [[TMP2]], [[TMP3]]
|
||||
// CHECK: [[TMP4:%.*]] = and <1 x i64> %a, %b
|
||||
// CHECK: [[TMP5:%.*]] = icmp ne <1 x i64> [[TMP4]], zeroinitializer
|
||||
// CHECK: [[VTST_I:%.*]] = sext <1 x i1> [[TMP5]] to <1 x i64>
|
||||
// CHECK: ret <1 x i64> [[VTST_I]]
|
||||
|
|
@ -36,11 +32,7 @@ uint64x1_t test_vtst_p64(poly64x1_t a, poly64x1_t b) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i64> @test_vtstq_p64(<2 x i64> %a, <2 x i64> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
|
||||
// CHECK: [[TMP4:%.*]] = and <2 x i64> [[TMP2]], [[TMP3]]
|
||||
// CHECK: [[TMP4:%.*]] = and <2 x i64> %a, %b
|
||||
// CHECK: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer
|
||||
// CHECK: [[VTST_I:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>
|
||||
// CHECK: ret <2 x i64> [[VTST_I]]
|
||||
|
|
@ -49,15 +41,9 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define <1 x i64> @test_vbsl_p64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <1 x i64> %c to <8 x i8>
|
||||
// CHECK: [[VBSL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
|
||||
// CHECK: [[VBSL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64>
|
||||
// CHECK: [[VBSL2_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64>
|
||||
// CHECK: [[VBSL3_I:%.*]] = and <1 x i64> [[VBSL_I]], [[VBSL1_I]]
|
||||
// CHECK: [[TMP3:%.*]] = xor <1 x i64> [[VBSL_I]], <i64 -1>
|
||||
// CHECK: [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], [[VBSL2_I]]
|
||||
// CHECK: [[VBSL3_I:%.*]] = and <1 x i64> %a, %b
|
||||
// CHECK: [[TMP3:%.*]] = xor <1 x i64> %a, <i64 -1>
|
||||
// CHECK: [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c
|
||||
// CHECK: [[VBSL5_I:%.*]] = or <1 x i64> [[VBSL3_I]], [[VBSL4_I]]
|
||||
// CHECK: ret <1 x i64> [[VBSL5_I]]
|
||||
poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {
|
||||
|
|
@ -65,15 +51,9 @@ poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {
|
|||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i64> @test_vbslq_p64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <2 x i64> %c to <16 x i8>
|
||||
// CHECK: [[VBSL_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
|
||||
// CHECK: [[VBSL1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>
|
||||
// CHECK: [[VBSL2_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
|
||||
// CHECK: [[VBSL3_I:%.*]] = and <2 x i64> [[VBSL_I]], [[VBSL1_I]]
|
||||
// CHECK: [[TMP3:%.*]] = xor <2 x i64> [[VBSL_I]], <i64 -1, i64 -1>
|
||||
// CHECK: [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], [[VBSL2_I]]
|
||||
// CHECK: [[VBSL3_I:%.*]] = and <2 x i64> %a, %b
|
||||
// CHECK: [[TMP3:%.*]] = xor <2 x i64> %a, <i64 -1, i64 -1>
|
||||
// CHECK: [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c
|
||||
// CHECK: [[VBSL5_I:%.*]] = or <2 x i64> [[VBSL3_I]], [[VBSL4_I]]
|
||||
// CHECK: ret <2 x i64> [[VBSL5_I]]
|
||||
poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
|
||||
|
|
|
|||
|
|
@ -3,133 +3,85 @@
|
|||
#include <arm_neon.h>
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRNDA_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> [[VRNDA_V_I]]) #2
|
||||
// CHECK: [[VRNDA_V2_I:%.*]] = bitcast <2 x float> [[VRNDA_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDA_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRNDA_V1_I]]
|
||||
float32x2_t test_vrnda_f32(float32x2_t a) {
|
||||
return vrnda_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDAQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> [[VRNDAQ_V_I]]) #2
|
||||
// CHECK: [[VRNDAQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDAQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDAQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDAQ_V1_I]]
|
||||
float32x4_t test_vrndaq_f32(float32x4_t a) {
|
||||
return vrndaq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrndm_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> [[VRNDM_V_I]]) #2
|
||||
// CHECK: [[VRNDM_V2_I:%.*]] = bitcast <2 x float> [[VRNDM_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRNDM_V1_I]]
|
||||
float32x2_t test_vrndm_f32(float32x2_t a) {
|
||||
return vrndm_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndmq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> [[VRNDMQ_V_I]]) #2
|
||||
// CHECK: [[VRNDMQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDMQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDMQ_V1_I]]
|
||||
float32x4_t test_vrndmq_f32(float32x4_t a) {
|
||||
return vrndmq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrndn_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRNDN_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> [[VRNDN_V_I]]) #2
|
||||
// CHECK: [[VRNDN_V2_I:%.*]] = bitcast <2 x float> [[VRNDN_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDN_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRNDN_V1_I]]
|
||||
float32x2_t test_vrndn_f32(float32x2_t a) {
|
||||
return vrndn_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndnq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDNQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> [[VRNDNQ_V_I]]) #2
|
||||
// CHECK: [[VRNDNQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDNQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDNQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDNQ_V1_I]]
|
||||
float32x4_t test_vrndnq_f32(float32x4_t a) {
|
||||
return vrndnq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrndp_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRNDP_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> [[VRNDP_V_I]]) #2
|
||||
// CHECK: [[VRNDP_V2_I:%.*]] = bitcast <2 x float> [[VRNDP_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDP_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRNDP_V1_I]]
|
||||
float32x2_t test_vrndp_f32(float32x2_t a) {
|
||||
return vrndp_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndpq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDPQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> [[VRNDPQ_V_I]]) #2
|
||||
// CHECK: [[VRNDPQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDPQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDPQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDPQ_V1_I]]
|
||||
float32x4_t test_vrndpq_f32(float32x4_t a) {
|
||||
return vrndpq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrndx_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRNDX_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> [[VRNDX_V_I]]) #2
|
||||
// CHECK: [[VRNDX_V2_I:%.*]] = bitcast <2 x float> [[VRNDX_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRNDX_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRNDX_V1_I]]
|
||||
float32x2_t test_vrndx_f32(float32x2_t a) {
|
||||
return vrndx_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndxq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDXQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> [[VRNDXQ_V_I]]) #2
|
||||
// CHECK: [[VRNDXQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDXQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDXQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDXQ_V1_I]]
|
||||
float32x4_t test_vrndxq_f32(float32x4_t a) {
|
||||
return vrndxq_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vrnd_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VRND_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> [[VRND_V_I]]) #2
|
||||
// CHECK: [[VRND_V2_I:%.*]] = bitcast <2 x float> [[VRND_V1_I]] to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[VRND_V2_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP1]]
|
||||
// CHECK: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x float> [[VRND_V1_I]]
|
||||
float32x2_t test_vrnd_f32(float32x2_t a) {
|
||||
return vrnd_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vrndq_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VRNDQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> [[VRNDQ_V_I]]) #2
|
||||
// CHECK: [[VRNDQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDQ_V1_I]] to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[VRNDQ_V2_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP1]]
|
||||
// CHECK: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x float> [[VRNDQ_V1_I]]
|
||||
float32x4_t test_vrndq_f32(float32x4_t a) {
|
||||
return vrndq_f32(a);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,26 +8,14 @@
|
|||
#include <arm_neon.h>
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_fma_order(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %accum to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %lhs to <8 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <2 x float> %rhs to <8 x i8>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
|
||||
// CHECK: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP2]] to <2 x float>
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP4]], <2 x float> [[TMP5]], <2 x float> [[TMP3]]) #2
|
||||
// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %rhs, <2 x float> %accum) #2
|
||||
// CHECK: ret <2 x float> [[TMP6]]
|
||||
float32x2_t test_fma_order(float32x2_t accum, float32x2_t lhs, float32x2_t rhs) {
|
||||
return vfma_f32(accum, lhs, rhs);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_fmaq_order(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %accum to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %lhs to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <4 x float> %rhs to <16 x i8>
|
||||
// CHECK: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
|
||||
// CHECK: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <4 x float>
|
||||
// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]], <4 x float> [[TMP3]]) #2
|
||||
// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %rhs, <4 x float> %accum) #2
|
||||
// CHECK: ret <4 x float> [[TMP6]]
|
||||
float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
|
||||
return vfmaq_f32(accum, lhs, rhs);
|
||||
|
|
|
|||
|
|
@ -3,53 +3,29 @@
|
|||
#include <arm_neon.h>
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vmaxnm_f32(<2 x float> %a, <2 x float> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
|
||||
// CHECK: [[VMAXNM_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VMAXNM_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
|
||||
// CHECK: [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> [[VMAXNM_V_I]], <2 x float> [[VMAXNM_V1_I]]) #2
|
||||
// CHECK: [[VMAXNM_V3_I:%.*]] = bitcast <2 x float> [[VMAXNM_V2_I]] to <8 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VMAXNM_V3_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP2]]
|
||||
// CHECK: [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %a, <2 x float> %b) #2
|
||||
// CHECK: ret <2 x float> [[VMAXNM_V2_I]]
|
||||
float32x2_t test_vmaxnm_f32(float32x2_t a, float32x2_t b) {
|
||||
return vmaxnm_f32(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
|
||||
// CHECK: [[VMAXNMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMAXNMQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
|
||||
// CHECK: [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> [[VMAXNMQ_V_I]], <4 x float> [[VMAXNMQ_V1_I]]) #2
|
||||
// CHECK: [[VMAXNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMAXNMQ_V2_I]] to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VMAXNMQ_V3_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP2]]
|
||||
// CHECK: [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %a, <4 x float> %b) #2
|
||||
// CHECK: ret <4 x float> [[VMAXNMQ_V2_I]]
|
||||
float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b) {
|
||||
return vmaxnmq_f32(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x float> @test_vminnm_f32(<2 x float> %a, <2 x float> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
|
||||
// CHECK: [[VMINNM_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VMINNM_V1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
|
||||
// CHECK: [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> [[VMINNM_V_I]], <2 x float> [[VMINNM_V1_I]]) #2
|
||||
// CHECK: [[VMINNM_V3_I:%.*]] = bitcast <2 x float> [[VMINNM_V2_I]] to <8 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[VMINNM_V3_I]] to <2 x float>
|
||||
// CHECK: ret <2 x float> [[TMP2]]
|
||||
// CHECK: [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %a, <2 x float> %b) #2
|
||||
// CHECK: ret <2 x float> [[VMINNM_V2_I]]
|
||||
float32x2_t test_vminnm_f32(float32x2_t a, float32x2_t b) {
|
||||
return vminnm_f32(a, b);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
|
||||
// CHECK: [[VMINNMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VMINNMQ_V1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
|
||||
// CHECK: [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> [[VMINNMQ_V_I]], <4 x float> [[VMINNMQ_V1_I]]) #2
|
||||
// CHECK: [[VMINNMQ_V3_I:%.*]] = bitcast <4 x float> [[VMINNMQ_V2_I]] to <16 x i8>
|
||||
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[VMINNMQ_V3_I]] to <4 x float>
|
||||
// CHECK: ret <4 x float> [[TMP2]]
|
||||
// CHECK: [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %a, <4 x float> %b) #2
|
||||
// CHECK: ret <4 x float> [[VMINNMQ_V2_I]]
|
||||
float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b) {
|
||||
return vminnmq_f32(a, b);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,144 +3,112 @@
|
|||
#include <arm_neon.h>
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvta_s32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTA_S32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTA_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> [[VCVTA_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTA_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTA_S32_V1_I]]
|
||||
int32x2_t test_vcvta_s32_f32(float32x2_t a) {
|
||||
return vcvta_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvta_u32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTA_U32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTA_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> [[VCVTA_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTA_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTA_U32_V1_I]]
|
||||
uint32x2_t test_vcvta_u32_f32(float32x2_t a) {
|
||||
return vcvta_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtaq_s32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTAQ_S32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTAQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> [[VCVTAQ_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTAQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTAQ_S32_V1_I]]
|
||||
int32x4_t test_vcvtaq_s32_f32(float32x4_t a) {
|
||||
return vcvtaq_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtaq_u32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTAQ_U32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTAQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> [[VCVTAQ_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTAQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTAQ_U32_V1_I]]
|
||||
uint32x4_t test_vcvtaq_u32_f32(float32x4_t a) {
|
||||
return vcvtaq_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtn_s32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTN_S32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTN_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> [[VCVTN_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTN_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTN_S32_V1_I]]
|
||||
int32x2_t test_vcvtn_s32_f32(float32x2_t a) {
|
||||
return vcvtn_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtn_u32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTN_U32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTN_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> [[VCVTN_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTN_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTN_U32_V1_I]]
|
||||
uint32x2_t test_vcvtn_u32_f32(float32x2_t a) {
|
||||
return vcvtn_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtnq_s32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTNQ_S32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTNQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> [[VCVTNQ_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTNQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTNQ_S32_V1_I]]
|
||||
int32x4_t test_vcvtnq_s32_f32(float32x4_t a) {
|
||||
return vcvtnq_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtnq_u32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTNQ_U32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTNQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> [[VCVTNQ_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTNQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTNQ_U32_V1_I]]
|
||||
uint32x4_t test_vcvtnq_u32_f32(float32x4_t a) {
|
||||
return vcvtnq_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtp_s32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTP_S32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTP_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> [[VCVTP_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTP_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTP_S32_V1_I]]
|
||||
int32x2_t test_vcvtp_s32_f32(float32x2_t a) {
|
||||
return vcvtp_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtp_u32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTP_U32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTP_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> [[VCVTP_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTP_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTP_U32_V1_I]]
|
||||
uint32x2_t test_vcvtp_u32_f32(float32x2_t a) {
|
||||
return vcvtp_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtpq_s32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTPQ_S32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTPQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> [[VCVTPQ_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTPQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTPQ_S32_V1_I]]
|
||||
int32x4_t test_vcvtpq_s32_f32(float32x4_t a) {
|
||||
return vcvtpq_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtpq_u32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTPQ_U32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTPQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> [[VCVTPQ_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTPQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTPQ_U32_V1_I]]
|
||||
uint32x4_t test_vcvtpq_u32_f32(float32x4_t a) {
|
||||
return vcvtpq_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtm_s32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTM_S32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTM_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> [[VCVTM_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTM_S32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTM_S32_V1_I]]
|
||||
int32x2_t test_vcvtm_s32_f32(float32x2_t a) {
|
||||
return vcvtm_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <2 x i32> @test_vcvtm_u32_f32(<2 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
|
||||
// CHECK: [[VCVTM_U32_V_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
|
||||
// CHECK: [[VCVTM_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> [[VCVTM_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTM_U32_V1_I:%.*]] = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %a) #2
|
||||
// CHECK: ret <2 x i32> [[VCVTM_U32_V1_I]]
|
||||
uint32x2_t test_vcvtm_u32_f32(float32x2_t a) {
|
||||
return vcvtm_u32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtmq_s32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTMQ_S32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTMQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> [[VCVTMQ_S32_V_I]]) #2
|
||||
// CHECK: [[VCVTMQ_S32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTMQ_S32_V1_I]]
|
||||
int32x4_t test_vcvtmq_s32_f32(float32x4_t a) {
|
||||
return vcvtmq_s32_f32(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: define <4 x i32> @test_vcvtmq_u32_f32(<4 x float> %a) #0 {
|
||||
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
|
||||
// CHECK: [[VCVTMQ_U32_V_I:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
|
||||
// CHECK: [[VCVTMQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> [[VCVTMQ_U32_V_I]]) #2
|
||||
// CHECK: [[VCVTMQ_U32_V1_I:%.*]] = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %a) #2
|
||||
// CHECK: ret <4 x i32> [[VCVTMQ_U32_V1_I]]
|
||||
uint32x4_t test_vcvtmq_u32_f32(float32x4_t a) {
|
||||
return vcvtmq_u32_f32(a);
|
||||
|
|
|
|||
Loading…
Reference in New Issue