forked from OSchip/llvm-project
[PowerPC] Fixup incomplete revert of test/CodeGen/PowerPC/tls-pic.ll
llvm-svn: 228467
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@ -19,32 +19,32 @@ entry:
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; OPT0-LABEL: main:
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; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
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; OPT0: addi 3, [[REG]], a@got@tlsld@l
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; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l
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; OPT0: bl __tls_get_addr(a@tlsld)
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; OPT0-NEXT: nop
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; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
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; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
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; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l
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; OPT0-32-LABEL: main
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; OPT0-32: addi 3, {{[0-9]+}}, a@got@tlsld
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; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld
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; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT
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; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
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; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; OPT1-32-LABEL: main
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; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld
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; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT
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; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha
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; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; OPT1-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l
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; Test peephole optimization for thread-local storage using the
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; local dynamic model.
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; OPT1-LABEL: main:
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; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha
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; OPT1: addi 3, [[REG]], a@got@tlsld@l
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; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l
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; OPT1: bl __tls_get_addr(a@tlsld)
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; OPT1-NEXT: nop
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; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha
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; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
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; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]])
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; Test correct assembly code generation for thread-local storage using
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; the general dynamic model.
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