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Pre-commit test case for trunc+lshr+load folds 

This is a pre-commit of test cases relevant for D117406.

@srl_load_narrowing1 is showing a pattern that could be folded into
a more narrow load.

@srl_load_narrowing2 is showing a similar pattern that happens to
be optimized already, but that happens in two steps (first triggering
a combine based on SRL and later another combine based on TRUNCATE).

Differential Revision: https://reviews.llvm.org/D117588
This commit is contained in:
Bjorn Pettersson 2022-01-18 19:48:35 +01:00
parent 3e6be0241b
commit 12a499eb00
1 changed files with 27 additions and 0 deletions
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27
llvm/test/CodeGen/X86/shift-folding.ll
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@ -83,3 +83,30 @@ define i32 @overshift(i32 %a) {
ret i32 %xor
}
; Should be possible to adjust the pointer and narrow the load to 16 bits.
define i16 @srl_load_narrowing1(i32* %arg) {
; CHECK-LABEL: srl_load_narrowing1:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: shrl $8, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
%tmp1 = load i32, i32* %arg, align 1
%tmp2 = lshr i32 %tmp1, 8
%tmp3 = trunc i32 %tmp2 to i16
ret i16 %tmp3
}
define i16 @srl_load_narrowing2(i32* %arg) {
; CHECK-LABEL: srl_load_narrowing2:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movzbl 3(%eax), %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
%tmp1 = load i32, i32* %arg, align 1
%tmp2 = lshr i32 %tmp1, 24
%tmp3 = trunc i32 %tmp2 to i16
ret i16 %tmp3
}