forked from OSchip/llvm-project
AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds the additional non-allocatable TTMP registers. There's no point in allocating SReg_128 vregs. This shrinks the size of the classes regalloc needs to consider, which is usually good. llvm-svn: 374284
This commit is contained in:
Matt Arsenault
parent
0a84576262
commit
12994a70cf
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@ -643,7 +643,7 @@ static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
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case 3:
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return AMDGPU::SGPR_96RegClassID;
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case 4:
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return AMDGPU::SReg_128RegClassID;
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return AMDGPU::SGPR_128RegClassID;
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case 5:
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return AMDGPU::SGPR_160RegClassID;
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case 8:
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@ -783,7 +783,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
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SDValue RC, SubReg0, SubReg1;
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SDLoc DL(N);
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if (N->getValueType(0) == MVT::i128) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32);
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RC = CurDAG->getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32);
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} else if (N->getValueType(0) == MVT::i64) {
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@ -1052,7 +1052,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
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return true;
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if (MFI->ScratchRSrcReg != AMDGPU::PRIVATE_RSRC_REG &&
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!AMDGPU::SReg_128RegClass.contains(MFI->ScratchRSrcReg)) {
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!AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
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return diagnoseRegisterClass(YamlMFI.ScratchRSrcReg);
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}
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@ -1101,7 +1101,7 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
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if (YamlMFI.ArgInfo &&
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(parseAndCheckArgument(YamlMFI.ArgInfo->PrivateSegmentBuffer,
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AMDGPU::SReg_128RegClass,
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AMDGPU::SGPR_128RegClass,
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MFI->ArgInfo.PrivateSegmentBuffer, 4, 0) ||
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parseAndCheckArgument(YamlMFI.ArgInfo->DispatchPtr,
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AMDGPU::SReg_64RegClass, MFI->ArgInfo.DispatchPtr,
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@ -125,10 +125,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
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addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
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addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
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addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
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addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
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addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
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@ -10494,7 +10494,7 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
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// Combine the constants and the pointer.
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const SDValue Ops1[] = {
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DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
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DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
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Ptr,
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DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
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SubRegHi,
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@ -10524,7 +10524,7 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
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SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
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const SDValue Ops[] = {
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DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
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DAG.getTargetConstant(AMDGPU::SGPR_128RegClassID, DL, MVT::i32),
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PtrLo,
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DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
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PtrHi,
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@ -10567,7 +10567,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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RC = &AMDGPU::SReg_96RegClass;
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break;
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case 128:
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RC = &AMDGPU::SReg_128RegClass;
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RC = &AMDGPU::SGPR_128RegClass;
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break;
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case 160:
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RC = &AMDGPU::SReg_160RegClass;
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@ -4267,7 +4267,7 @@ emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
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Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
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Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
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// Beginning of the loop, read the next Rsrc variant.
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BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
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@ -4406,7 +4406,7 @@ extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
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Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
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Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
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Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
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uint64_t RsrcDataFormat = TII.getDefaultRsrcDataFormat();
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// Zero64 = 0
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@ -6178,7 +6178,7 @@ bool SIInstrInfo::isBufferSMRD(const MachineInstr &MI) const {
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return false;
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const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
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return RCID == AMDGPU::SReg_128RegClassID;
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return RI.getRegClass(RCID)->hasSubClassEq(&AMDGPU::SGPR_128RegClass);
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}
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bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
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@ -1120,7 +1120,7 @@ SILoadStoreOptimizer::getTargetRegisterClass(const CombineInfo &CI) {
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case 2:
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return &AMDGPU::SReg_64_XEXECRegClass;
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case 4:
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return &AMDGPU::SReg_128RegClass;
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return &AMDGPU::SGPR_128RegClass;
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case 8:
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return &AMDGPU::SReg_256RegClass;
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case 16:
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@ -189,7 +189,7 @@ unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
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const SIRegisterInfo &TRI) {
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ArgInfo.PrivateSegmentBuffer =
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ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
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NumUserSGPRs += 4;
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return ArgInfo.PrivateSegmentBuffer.getRegister();
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}
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@ -123,7 +123,7 @@ unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
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unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
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return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
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return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass);
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}
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static unsigned findPrivateSegmentWaveByteOffsetRegIndex(unsigned RegCount) {
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@ -1546,7 +1546,7 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
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case 96:
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return &AMDGPU::SReg_96RegClass;
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case 128:
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return &AMDGPU::SReg_128RegClass;
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return &AMDGPU::SGPR_128RegClass;
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case 160:
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return &AMDGPU::SReg_160RegClass;
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case 256:
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@ -1576,7 +1576,7 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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case 3:
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return &AMDGPU::SReg_96RegClass;
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case 4:
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return &AMDGPU::SReg_128RegClass;
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return &AMDGPU::SGPR_128RegClass;
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case 5:
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return &AMDGPU::SReg_160RegClass;
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case 8:
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@ -1966,7 +1966,7 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
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&AMDGPU::SReg_96RegClass;
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case 128:
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return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_128RegClass :
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&AMDGPU::SReg_128RegClass;
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&AMDGPU::SGPR_128RegClass;
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case 160:
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return RB.getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_160RegClass :
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&AMDGPU::SReg_160RegClass;
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@ -1990,9 +1990,12 @@ SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
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const TargetRegisterClass *
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SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
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const MachineRegisterInfo &MRI) const {
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if (const RegisterBank *RB = MRI.getRegBankOrNull(MO.getReg()))
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const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
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if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
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return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
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return nullptr;
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const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>();
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return getAllocatableClass(RC);
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}
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unsigned SIRegisterInfo::getVCC() const {
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@ -529,6 +529,7 @@ def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64], 32,
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def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32,
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(add SGPR_128, TTMP_128)> {
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let AllocationPriority = 15;
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let isAllocatable = 0;
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}
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} // End CopyCost = 2
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@ -143,7 +143,7 @@ body: |
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; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
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%0:sgpr(s64) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = COPY $sgpr2_sgpr3
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@ -146,7 +146,7 @@ body: |
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
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; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<2 x s16>) = COPY $sgpr0
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%1:sgpr(<2 x s16>) = COPY $sgpr1
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@ -192,7 +192,7 @@ body: |
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; GCN-LABEL: name: test_concat_vectors_s_v8s16_s_v4s16_s_v4s16
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
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%1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
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@ -350,8 +350,8 @@ body: |
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN-LABEL: name: test_concat_vectors_s_v12s16_s_v8s16_s_v8s16
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<8 x s16>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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@ -461,7 +461,7 @@ body: |
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; GCN-LABEL: name: test_concat_vectors_s_v4s32_s_v2s32_s_v2s32
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; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
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; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
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%1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
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@ -524,8 +524,8 @@ body: |
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN-LABEL: name: test_concat_vectors_s_v8s32_s_v4s32_s_v4s32
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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@ -596,8 +596,8 @@ body: |
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN-LABEL: name: test_concat_vectors_s_v4s64_s_v2s64_s_v2s64
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
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; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
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%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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@ -656,10 +656,10 @@ body: |
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr12_sgpr13_sgpr14_sgpr15
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; GCN-LABEL: name: test_concat_vectors_s_v8s64_s_v2s64_s_v2s64_s_v2s64_s_v2s64
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; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[COPY2:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
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; GCN: [[COPY3:%[0-9]+]]:sreg_128 = COPY $sgpr12_sgpr13_sgpr14_sgpr15
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; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
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; GCN: [[COPY2:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
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; GCN: [[COPY3:%[0-9]+]]:sgpr_128 = COPY $sgpr12_sgpr13_sgpr14_sgpr15
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_512 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7, [[COPY2]], %subreg.sub8_sub9_sub10_sub11, [[COPY3]], %subreg.sub12_sub13_sub14_sub15
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
|
|
@ -680,8 +680,8 @@ body: |
|
|||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
|
||||
; GCN-LABEL: name: test_concat_vectors_s_v4p1_s_v2p1_s_v2p1
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(<2 x p1>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
|
|
@ -702,7 +702,7 @@ body: |
|
|||
; GCN-LABEL: name: test_concat_vectors_s_v4p3_s_v2p3_s_v2p3
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(<2 x p3>) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(<2 x p3>) = COPY $sgpr2_sgpr3
|
||||
|
|
|
|||
|
|
@ -256,9 +256,9 @@ body: |
|
|||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
|
||||
; CHECK-LABEL: name: insert_s_s128_s_s64_0
|
||||
; CHECK: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1
|
||||
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||||
|
|
@ -291,9 +291,9 @@ body: |
|
|||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5
|
||||
; CHECK-LABEL: name: insert_s_s128_s_s64_64
|
||||
; CHECK: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub2_sub3
|
||||
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:sgpr(s64) = COPY $sgpr4_sgpr5
|
||||
|
|
@ -368,7 +368,7 @@ body: |
|
|||
; CHECK-LABEL: name: insert_s_s128_s_s96_0
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub0_sub1_sub2 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2
|
||||
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||||
|
|
@ -388,7 +388,7 @@ body: |
|
|||
; CHECK-LABEL: name: insert_s_s128_s_s96_32
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr_128_with_sub1_sub2_sub3 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sreg_96 = COPY $sgpr6_sgpr7_sgpr8
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sgpr_128 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub1_sub2_sub3
|
||||
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:sgpr(s96) = COPY $sgpr6_sgpr7_sgpr8
|
||||
|
|
@ -468,7 +468,7 @@ body: |
|
|||
|
||||
; CHECK-LABEL: name: insert_s_s256_s_s128_0
|
||||
; CHECK: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr8_sgpr9_sgpr10_sgpr11
|
||||
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:sreg_256 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0_sub1_sub2_sub3
|
||||
; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
|
||||
%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||||
|
|
|
|||
|
|
@ -208,23 +208,23 @@ body: |
|
|||
; GFX6-LABEL: name: load_constant_v4s32_align4
|
||||
; GFX6: liveins: $sgpr0_sgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX7-LABEL: name: load_constant_v4s32_align4
|
||||
; GFX7: liveins: $sgpr0_sgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX7: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX8-LABEL: name: load_constant_v4s32_align4
|
||||
; GFX8: liveins: $sgpr0_sgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX10-LABEL: name: load_constant_v4s32_align4
|
||||
; GFX10: liveins: $sgpr0_sgpr1
|
||||
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX10: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
%0:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(<4 x s32>) = G_LOAD %0 :: (load 16, align 4, addrspace 4)
|
||||
|
|
@ -322,23 +322,23 @@ body: |
|
|||
; GFX6-LABEL: name: load_constant_v2s64
|
||||
; GFX6: liveins: $sgpr0_sgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX7-LABEL: name: load_constant_v2s64
|
||||
; GFX7: liveins: $sgpr0_sgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX7: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX8-LABEL: name: load_constant_v2s64
|
||||
; GFX8: liveins: $sgpr0_sgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
; GFX10-LABEL: name: load_constant_v2s64
|
||||
; GFX10: liveins: $sgpr0_sgpr1
|
||||
; GFX10: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX10: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0, 0 :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[S_LOAD_DWORDX4_IMM]]
|
||||
%0:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(<2 x s64>) = G_LOAD %0 :: (load 16, align 4, addrspace 4)
|
||||
|
|
@ -360,22 +360,22 @@ body: |
|
|||
; GFX6-LABEL: name: load_constant_v2p1
|
||||
; GFX6: liveins: $sgpr0_sgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sreg_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sgpr_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<2 x p1>)
|
||||
; GFX7-LABEL: name: load_constant_v2p1
|
||||
; GFX7: liveins: $sgpr0_sgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sreg_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sgpr_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<2 x p1>)
|
||||
; GFX8-LABEL: name: load_constant_v2p1
|
||||
; GFX8: liveins: $sgpr0_sgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sreg_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sgpr_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<2 x p1>)
|
||||
; GFX10-LABEL: name: load_constant_v2p1
|
||||
; GFX10: liveins: $sgpr0_sgpr1
|
||||
; GFX10: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sreg_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sgpr_128(<2 x p1>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<2 x p1>)
|
||||
%0:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(<2 x p1>) = G_LOAD %0 :: (load 16, align 4, addrspace 4)
|
||||
|
|
@ -397,22 +397,22 @@ body: |
|
|||
; GFX6-LABEL: name: load_constant_s128_align4
|
||||
; GFX6: liveins: $sgpr0_sgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sreg_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sgpr_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](s128)
|
||||
; GFX7-LABEL: name: load_constant_s128_align4
|
||||
; GFX7: liveins: $sgpr0_sgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sreg_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sgpr_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](s128)
|
||||
; GFX8-LABEL: name: load_constant_s128_align4
|
||||
; GFX8: liveins: $sgpr0_sgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sreg_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sgpr_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](s128)
|
||||
; GFX10-LABEL: name: load_constant_s128_align4
|
||||
; GFX10: liveins: $sgpr0_sgpr1
|
||||
; GFX10: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sreg_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sgpr_128(s128) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](s128)
|
||||
%0:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s128) = G_LOAD %0 :: (load 16, align 4, addrspace 4)
|
||||
|
|
@ -660,22 +660,22 @@ body: |
|
|||
; GFX6-LABEL: name: load_constant_v8s16
|
||||
; GFX6: liveins: $sgpr0_sgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sreg_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: [[LOAD:%[0-9]+]]:sgpr_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX6: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<8 x s16>)
|
||||
; GFX7-LABEL: name: load_constant_v8s16
|
||||
; GFX7: liveins: $sgpr0_sgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sreg_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: [[LOAD:%[0-9]+]]:sgpr_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX7: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<8 x s16>)
|
||||
; GFX8-LABEL: name: load_constant_v8s16
|
||||
; GFX8: liveins: $sgpr0_sgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sreg_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: [[LOAD:%[0-9]+]]:sgpr_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX8: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<8 x s16>)
|
||||
; GFX10-LABEL: name: load_constant_v8s16
|
||||
; GFX10: liveins: $sgpr0_sgpr1
|
||||
; GFX10: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sreg_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: [[LOAD:%[0-9]+]]:sgpr_128(<8 x s16>) = G_LOAD [[COPY]](p4) :: (load 16, align 4, addrspace 4)
|
||||
; GFX10: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[LOAD]](<8 x s16>)
|
||||
%0:sgpr(p4) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(<8 x s16>) = G_LOAD %0 :: (load 16, align 4, addrspace 4)
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@ body: |
|
|||
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr2
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
|
|
@ -248,7 +248,7 @@ body: |
|
|||
; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr2_sgpr3
|
||||
|
|
@ -420,8 +420,8 @@ body: |
|
|||
|
||||
; GCN-LABEL: name: test_merge_values_s_s256_s_s128_s_s128
|
||||
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY $sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_256 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1_sub2_sub3, [[COPY1]], %subreg.sub4_sub5_sub6_sub7
|
||||
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY [[REG_SEQUENCE]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ body: |
|
|||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN-LABEL: name: trunc_sgpr_s128_to_s16
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
|
||||
; GCN: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%0:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
|
|
@ -163,7 +163,7 @@ body: |
|
|||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN-LABEL: name: trunc_sgpr_s256_to_s128
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_256 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_128 = COPY [[COPY]].sub0_sub1_sub2_sub3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sgpr_128 = COPY [[COPY]].sub0_sub1_sub2_sub3
|
||||
; GCN: S_ENDPGM 0, implicit [[COPY1]]
|
||||
%0:sgpr(s256) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
|
||||
%1:sgpr(s128) = G_TRUNC %0
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ body: |
|
|||
|
||||
; GCN-LABEL: name: test_unmerge_values_s_s32_s_s32_s32_s_s32_s_s128
|
||||
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub0
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub1
|
||||
; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY [[COPY]].sub2
|
||||
|
|
@ -164,7 +164,7 @@ body: |
|
|||
|
||||
; GCN-LABEL: name: test_unmerge_values_s_s64_s_s64_s_s128
|
||||
; GCN: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY:%[0-9]+]]:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; GCN: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub0_sub1
|
||||
; GCN: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY [[COPY]].sub2_sub3
|
||||
; GCN: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; UNPACKED: S_ENDPGM 0
|
||||
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16
|
||||
|
|
@ -26,7 +26,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -43,7 +43,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
|
|||
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)
|
||||
; UNPACKED: S_ENDPGM 0
|
||||
; PACKED-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16
|
||||
|
|
@ -55,7 +55,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
|
|||
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7 + 4095, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
|
||||
|
|
@ -73,7 +73,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY7]], [[COPY4]], implicit $exec
|
||||
|
|
@ -90,7 +90,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -109,7 +109,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; UNPACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; UNPACKED: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; UNPACKED: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 [[COPY8]], [[COPY4]], implicit $exec
|
||||
|
|
@ -129,7 +129,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; PACKED: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
|
|
@ -172,7 +172,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; UNPACKED: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY11]], implicit $exec
|
||||
; UNPACKED: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; UNPACKED: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; UNPACKED: BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; UNPACKED: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; UNPACKED: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -210,7 +210,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; PACKED: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY9]], implicit $exec
|
||||
; PACKED: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; PACKED: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; PACKED: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -234,7 +234,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
|
||||
|
|
@ -251,7 +251,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
|
|
@ -269,7 +269,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
|
||||
; UNPACKED: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_1]]
|
||||
|
|
@ -286,7 +286,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: S_ENDPGM 0
|
||||
|
|
@ -305,7 +305,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; UNPACKED: %11:vgpr_32, dead %21:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -324,7 +324,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -346,7 +346,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095
|
||||
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -366,7 +366,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095
|
||||
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -388,7 +388,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; UNPACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; UNPACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; UNPACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
|
||||
; UNPACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; UNPACKED: %11:vgpr_32, dead %22:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -408,7 +408,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; PACKED: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; PACKED: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; PACKED: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
|
||||
; PACKED: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; PACKED: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -458,7 +458,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; UNPACKED: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; UNPACKED: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY12]], implicit $exec
|
||||
; UNPACKED: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; UNPACKED: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; UNPACKED: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; UNPACKED: BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; UNPACKED: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; UNPACKED: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -499,7 +499,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; PACKED: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; PACKED: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY10]], implicit $exec
|
||||
; PACKED: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; PACKED: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; PACKED: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; PACKED: BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact [[REG_SEQUENCE1]], %13, [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; PACKED: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; PACKED: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -30,7 +30,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
|
|||
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
|
||||
|
|
@ -49,7 +49,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -70,7 +70,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2
|
||||
; CHECK: BUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -92,7 +92,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -131,7 +131,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY11]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE4]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -156,7 +156,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
|
|
@ -176,7 +176,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
|
||||
; CHECK: BUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
|
|
@ -197,7 +197,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
|
|
@ -221,7 +221,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
|
|
@ -245,7 +245,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
|
|
@ -293,7 +293,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse
|
|||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY12]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE1]], %15, [[REG_SEQUENCE4]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -33,7 +33,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr6
|
||||
; CHECK: [[COPY5:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr7
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]]
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
|
|
@ -70,7 +70,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE3]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -97,7 +97,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
||||
|
|
@ -144,7 +144,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr
|
|||
; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec
|
||||
; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc
|
||||
|
|
@ -172,7 +172,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1)
|
||||
|
|
@ -190,7 +190,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
|
||||
|
|
@ -208,7 +208,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3)
|
||||
|
|
@ -226,7 +226,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4)
|
||||
|
|
@ -244,7 +244,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6)
|
||||
|
|
@ -262,7 +262,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5)
|
||||
|
|
@ -280,7 +280,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7)
|
||||
|
|
@ -299,7 +299,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -320,7 +320,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2
|
||||
; CHECK: BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -342,7 +342,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -361,7 +361,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom TargetCustom7, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
%val.trunc = trunc i32 %val to i8
|
||||
|
|
@ -380,7 +380,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
%val.trunc = trunc i32 %val to i16
|
||||
|
|
@ -399,7 +399,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -417,7 +417,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
|
||||
|
|
@ -436,7 +436,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
|
||||
; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -473,7 +473,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY9]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -497,7 +497,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_v
|
|||
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
|
||||
|
|
@ -514,7 +514,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_v
|
|||
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4096, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -533,7 +533,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -555,7 +555,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -577,7 +577,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -598,7 +598,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -616,7 +616,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr5
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: S_ENDPGM 0
|
||||
|
|
@ -635,7 +635,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 16
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -657,7 +657,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4095
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -679,7 +679,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
|
||||
; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
|
||||
; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]]
|
||||
; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec
|
||||
|
|
@ -721,7 +721,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
|
|||
; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY9]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE3]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
@ -764,7 +764,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr
|
|||
; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1
|
||||
; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec
|
||||
; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
|
||||
; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE3]], [[COPY5]], 904, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 5000, align 1, addrspace 4)
|
||||
; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
|
||||
; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ define amdgpu_cs void @mmo_offsets0(<4 x i32> addrspace(6)* inreg noalias derefe
|
|||
; GCN: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1
|
||||
; GCN: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sreg_128 = S_LOAD_DWORDX4_IMM killed [[REG_SEQUENCE]], 0, 0, 0 :: (dereferenceable invariant load 16 from %ir.arg0, addrspace 6)
|
||||
; GCN: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM killed [[REG_SEQUENCE]], 0, 0, 0 :: (dereferenceable invariant load 16 from %ir.arg0, addrspace 6)
|
||||
; GCN: [[BUFFER_LOAD_DWORDX4_OFFSET:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7 + 16, align 1, addrspace 4)
|
||||
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
; GCN: [[BUFFER_LOAD_DWORDX4_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_IDXEN [[V_MOV_B32_e32_]], [[S_LOAD_DWORDX4_IMM]], [[S_MOV_B32_]], 16, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
|
||||
|
|
|
|||
|
|
@ -12,10 +12,10 @@ body: |
|
|||
%1:vgpr_32 = COPY %0
|
||||
INLINEASM &"; %1", 1, 327690, def %1, 2147483657, %1(tied-def 3)
|
||||
%2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
|
||||
undef %3.sub0:sreg_128 = COPY %0
|
||||
%3.sub1:sreg_128 = COPY %0
|
||||
%3.sub2:sreg_128 = COPY %0
|
||||
%4:sreg_128 = COPY %3
|
||||
undef %3.sub0:sgpr_128 = COPY %0
|
||||
%3.sub1:sgpr_128 = COPY %0
|
||||
%3.sub2:sgpr_128 = COPY %0
|
||||
%4:sgpr_128 = COPY %3
|
||||
%5:vgpr_32 = V_MOV_B32_e32 -64, implicit $exec
|
||||
%6:vreg_128 = COPY %4
|
||||
%7:sreg_32_xm0 = S_AND_B32 target-flags(amdgpu-gotprel) 1, %2.sub0, implicit-def dead $scc
|
||||
|
|
@ -30,7 +30,7 @@ body: |
|
|||
%14:vgpr_32 = V_AND_B32_e32 1, %13, implicit $exec
|
||||
%15:sreg_64_xexec = V_CMP_EQ_U32_e64 0, %14, implicit $exec
|
||||
%16:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %15, implicit $exec
|
||||
BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
|
||||
BUFFER_STORE_DWORD_OFFEN_exact %16, undef %17:vgpr_32, undef %18:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into constant-pool, align 1, addrspace 4)
|
||||
S_ENDPGM 0
|
||||
|
||||
bb.2:
|
||||
|
|
@ -44,10 +44,10 @@ body: |
|
|||
|
||||
bb.3:
|
||||
successors: %bb.4
|
||||
undef %22.sub0:sreg_128 = COPY %8
|
||||
%22.sub1:sreg_128 = COPY %8
|
||||
%22.sub2:sreg_128 = COPY %8
|
||||
%23:sreg_128 = COPY %22
|
||||
undef %22.sub0:sgpr_128 = COPY %8
|
||||
%22.sub1:sgpr_128 = COPY %8
|
||||
%22.sub2:sgpr_128 = COPY %8
|
||||
%23:sgpr_128 = COPY %22
|
||||
%24:vreg_128 = COPY %23
|
||||
%10:vreg_128 = COPY %24
|
||||
|
||||
|
|
@ -78,7 +78,7 @@ body: |
|
|||
|
||||
bb.8:
|
||||
successors: %bb.10
|
||||
%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
|
||||
%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
|
||||
%34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
|
||||
%35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
|
||||
%28:vgpr_32 = COPY %35
|
||||
|
|
|
|||
|
|
@ -10,18 +10,18 @@ body: |
|
|||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
liveins: $sgpr4
|
||||
undef %0.sub2:sreg_128 = COPY $sgpr4
|
||||
undef %0.sub2:sgpr_128 = COPY $sgpr4
|
||||
%3 = IMPLICIT_DEF
|
||||
S_CBRANCH_SCC1 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
%0.sub0:sreg_128 = COPY %0.sub2
|
||||
%0.sub1:sreg_128 = COPY %0.sub2
|
||||
%1:sreg_128 = COPY %0
|
||||
%2:sreg_128 = COPY %0
|
||||
%0:sreg_128 = COPY %2
|
||||
%3:sreg_128 = COPY %1
|
||||
%0.sub0:sgpr_128 = COPY %0.sub2
|
||||
%0.sub1:sgpr_128 = COPY %0.sub2
|
||||
%1:sgpr_128 = COPY %0
|
||||
%2:sgpr_128 = COPY %0
|
||||
%0:sgpr_128 = COPY %2
|
||||
%3:sgpr_128 = COPY %1
|
||||
|
||||
bb.2:
|
||||
$sgpr1 = COPY %3
|
||||
|
|
|
|||
|
|
@ -42,10 +42,10 @@ body: |
|
|||
bb.3:
|
||||
successors: %bb.5(0x80000000)
|
||||
%8:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %9.sub0:sreg_128 = COPY %8
|
||||
%9.sub1:sreg_128 = COPY %8
|
||||
%9.sub2:sreg_128 = COPY %8
|
||||
%9.sub3:sreg_128 = COPY killed %8
|
||||
undef %9.sub0:sgpr_128 = COPY %8
|
||||
%9.sub1:sgpr_128 = COPY %8
|
||||
%9.sub2:sgpr_128 = COPY %8
|
||||
%9.sub3:sgpr_128 = COPY killed %8
|
||||
%10:vreg_128 = COPY killed %9
|
||||
%7:vreg_128 = COPY killed %10
|
||||
S_BRANCH %bb.5
|
||||
|
|
@ -53,11 +53,11 @@ body: |
|
|||
bb.4:
|
||||
successors: %bb.5(0x80000000)
|
||||
%11:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %12.sub0:sreg_128 = COPY %11
|
||||
%12.sub1:sreg_128 = COPY %11
|
||||
%12.sub2:sreg_128 = COPY %11
|
||||
%12.sub3:sreg_128 = COPY killed %11
|
||||
%13:sreg_128 = COPY killed %12
|
||||
undef %12.sub0:sgpr_128 = COPY %11
|
||||
%12.sub1:sgpr_128 = COPY %11
|
||||
%12.sub2:sgpr_128 = COPY %11
|
||||
%12.sub3:sgpr_128 = COPY killed %11
|
||||
%13:sgpr_128 = COPY killed %12
|
||||
%14:vreg_128 = COPY killed %13
|
||||
%7:vreg_128 = COPY killed %14
|
||||
|
||||
|
|
@ -83,7 +83,7 @@ body: |
|
|||
|
||||
bb.9:
|
||||
successors: %bb.10(0x80000000)
|
||||
%19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%19:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %18, undef %20:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%21:sreg_64 = V_CMP_NE_U32_e64 target-flags(amdgpu-gotprel) 0, killed %19.sub0, implicit $exec
|
||||
%22:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%23:sreg_64 = S_AND_B64 %22, %21, implicit-def dead $scc
|
||||
|
|
|
|||
|
|
@ -25,16 +25,16 @@ body: |
|
|||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
%0:sreg_64 = COPY $exec
|
||||
%1:sgpr_32 = S_MOV_B32 0
|
||||
undef %2.sub0:sreg_128 = COPY %1
|
||||
%2.sub1:sreg_128 = COPY %1
|
||||
%2.sub2:sreg_128 = COPY %1
|
||||
%2.sub3:sreg_128 = COPY %1
|
||||
undef %2.sub0:sgpr_128 = COPY %1
|
||||
%2.sub1:sgpr_128 = COPY %1
|
||||
%2.sub2:sgpr_128 = COPY %1
|
||||
%2.sub3:sgpr_128 = COPY %1
|
||||
$exec = S_WQM_B64 $exec, implicit-def dead $scc
|
||||
S_CBRANCH_SCC0 %bb.2, implicit undef $scc
|
||||
|
||||
bb.1:
|
||||
successors: %bb.3(0x80000000)
|
||||
%3:sreg_128 = COPY killed %2
|
||||
%3:sgpr_128 = COPY killed %2
|
||||
%4:vreg_128 = COPY killed %3
|
||||
%5:vreg_128 = COPY killed %4
|
||||
S_BRANCH %bb.3
|
||||
|
|
@ -47,7 +47,7 @@ body: |
|
|||
%10:vgpr_32 = V_CVT_U32_F32_e32 killed %9, implicit $exec
|
||||
%11:vgpr_32 = V_LSHLREV_B32_e32 1, killed %10, implicit $exec
|
||||
%12:sreg_64 = S_MOV_B64 0
|
||||
%13:sreg_128 = COPY killed %2
|
||||
%13:sgpr_128 = COPY killed %2
|
||||
%14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%15:vreg_128 = COPY killed %13
|
||||
%16:sreg_64 = COPY killed %12
|
||||
|
|
@ -68,7 +68,7 @@ body: |
|
|||
%23:vreg_128 = COPY killed %17
|
||||
%24:sreg_64 = COPY killed %16
|
||||
%25:vgpr_32 = V_OR_B32_e32 %22, %11, implicit $exec
|
||||
%26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%26:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %25, undef %27:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
%28:vgpr_32 = V_LSHRREV_B32_e32 30, killed %26.sub0, implicit $exec
|
||||
%29:vreg_128 = COPY killed %21
|
||||
%29.sub0:vreg_128 = COPY %1
|
||||
|
|
@ -257,7 +257,7 @@ body: |
|
|||
%109.sub5:sreg_256 = COPY %108
|
||||
%109.sub6:sreg_256 = COPY %108
|
||||
%109.sub7:sreg_256 = COPY killed %108
|
||||
%110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sreg_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sgpr_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%112:vgpr_32 = V_MUL_F32_e32 0, killed %110, implicit $exec
|
||||
%113:vgpr_32 = V_MUL_F32_e32 0, killed %112, implicit $exec
|
||||
%114:vgpr_32 = V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
|
|
|
|||
|
|
@ -12,9 +12,9 @@ registers:
|
|||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: sreg_256 }
|
||||
- { id: 4, class: sreg_128 }
|
||||
- { id: 4, class: sgpr_128 }
|
||||
- { id: 5, class: sreg_256 }
|
||||
- { id: 6, class: sreg_128 }
|
||||
- { id: 6, class: sgpr_128 }
|
||||
- { id: 7, class: sreg_512 }
|
||||
- { id: 9, class: vreg_512 }
|
||||
- { id: 11, class: vreg_512 }
|
||||
|
|
|
|||
|
|
@ -67,8 +67,8 @@ body: |
|
|||
successors: %bb.7(0x40000000), %bb.18(0x40000000)
|
||||
%9:vreg_128 = COPY killed %6
|
||||
%10:sreg_64 = COPY killed %5
|
||||
undef %11.sub2:sreg_128 = COPY %4
|
||||
%11.sub3:sreg_128 = COPY %3
|
||||
undef %11.sub2:sgpr_128 = COPY %4
|
||||
%11.sub3:sgpr_128 = COPY %3
|
||||
%12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
undef %13.sub1:vreg_128 = COPY %9.sub1
|
||||
%13.sub2:vreg_128 = COPY %9.sub2
|
||||
|
|
@ -161,7 +161,7 @@ body: |
|
|||
bb.18:
|
||||
successors: %bb.7(0x80000000)
|
||||
dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
|
||||
dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sreg_128, undef %65:sreg_32, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sgpr_128, undef %65:sreg_32, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
undef %66.sub1:vreg_128 = COPY %13.sub1
|
||||
%66.sub2:vreg_128 = COPY %13.sub2
|
||||
%67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
|
||||
|
|
|
|||
|
|
@ -109,11 +109,11 @@ body: |
|
|||
bb.9:
|
||||
successors: %bb.11(0x80000000)
|
||||
%32:sreg_32_xm0 = S_MOV_B32 0
|
||||
undef %33.sub0:sreg_128 = COPY %32
|
||||
%33.sub1:sreg_128 = COPY %32
|
||||
%33.sub2:sreg_128 = COPY %32
|
||||
%33.sub3:sreg_128 = COPY killed %32
|
||||
%34:sreg_128 = COPY killed %33
|
||||
undef %33.sub0:sgpr_128 = COPY %32
|
||||
%33.sub1:sgpr_128 = COPY %32
|
||||
%33.sub2:sgpr_128 = COPY %32
|
||||
%33.sub3:sgpr_128 = COPY killed %32
|
||||
%34:sgpr_128 = COPY killed %33
|
||||
%35:vreg_128 = COPY killed %34
|
||||
%31:vreg_128 = COPY killed %35
|
||||
S_BRANCH %bb.11
|
||||
|
|
@ -145,10 +145,10 @@ body: |
|
|||
%40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
|
||||
%41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec
|
||||
%42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec
|
||||
%43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sreg_128, 12, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sgpr_128, 12, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
|
||||
%46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
|
||||
%47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
|
||||
%47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
|
||||
%49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
|
||||
%50:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ registers:
|
|||
- { id: 3, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_32_xm0 }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: sreg_128 }
|
||||
- { id: 6, class: sgpr_128 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
|
|
@ -185,7 +185,7 @@ registers:
|
|||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -385,7 +385,7 @@ registers:
|
|||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -593,7 +593,7 @@ registers:
|
|||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_32_xm0 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: sreg_32_xm0 }
|
||||
- { id: 12, class: sreg_32_xm0 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
|
|||
|
|
@ -158,15 +158,15 @@ selected: false
|
|||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sreg_128, preferred-register: '' }
|
||||
- { id: 0, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 1, class: sreg_32_xm0, preferred-register: '%5' }
|
||||
- { id: 2, class: sreg_128, preferred-register: '' }
|
||||
- { id: 2, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 3, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 4, class: sreg_128, preferred-register: '' }
|
||||
- { id: 4, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 5, class: sreg_32_xm0, preferred-register: '%1' }
|
||||
- { id: 6, class: sreg_128, preferred-register: '' }
|
||||
- { id: 7, class: sreg_128, preferred-register: '' }
|
||||
- { id: 8, class: sreg_128, preferred-register: '' }
|
||||
- { id: 6, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 7, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 8, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 9, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 10, class: vgpr_32, preferred-register: '' }
|
||||
- { id: 11, class: vgpr_32, preferred-register: '' }
|
||||
|
|
@ -176,23 +176,23 @@ registers:
|
|||
- { id: 15, class: sreg_32, preferred-register: '' }
|
||||
- { id: 16, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 17, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 18, class: sreg_128, preferred-register: '' }
|
||||
- { id: 18, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 19, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 20, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 21, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 22, class: vreg_128, preferred-register: '' }
|
||||
- { id: 23, class: vgpr_32, preferred-register: '' }
|
||||
- { id: 24, class: sreg_128, preferred-register: '' }
|
||||
- { id: 24, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 25, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 26, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 27, class: sreg_128, preferred-register: '' }
|
||||
- { id: 27, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 28, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 29, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 30, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 31, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 32, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 33, class: sreg_32_xm0, preferred-register: '' }
|
||||
- { id: 34, class: sreg_128, preferred-register: '' }
|
||||
- { id: 34, class: sgpr_128, preferred-register: '' }
|
||||
- { id: 35, class: sreg_64, preferred-register: '' }
|
||||
- { id: 36, class: sreg_64, preferred-register: '' }
|
||||
- { id: 37, class: vgpr_32, preferred-register: '' }
|
||||
|
|
@ -291,7 +291,7 @@ body: |
|
|||
bb.3..lr.ph3410.preheader:
|
||||
successors: %bb.4(0x80000000)
|
||||
|
||||
dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sreg_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
|
||||
dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
%36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
|
||||
dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@ body: |
|
|||
bb.0:
|
||||
liveins: $sgpr0_sgpr1
|
||||
|
||||
%10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0, 0
|
||||
S_NOP 0, implicit-def %4:sreg_128, implicit %10.sub1:sreg_128
|
||||
%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0, 0
|
||||
S_NOP 0, implicit-def %4:sgpr_128, implicit %10.sub1:sgpr_128
|
||||
S_CBRANCH_SCC0 %bb.3, implicit undef $scc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
|
|
@ -21,14 +21,14 @@ body: |
|
|||
S_BRANCH %bb.3
|
||||
|
||||
bb.2:
|
||||
%8:sreg_32_xm0 = COPY %4.sub1:sreg_128
|
||||
%7:sreg_32_xm0 = COPY %10.sub1:sreg_128
|
||||
%8:sreg_32_xm0 = COPY %4.sub1:sgpr_128
|
||||
%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
|
||||
S_BRANCH %bb.4
|
||||
|
||||
bb.3:
|
||||
%10:sreg_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0, 0
|
||||
%7:sreg_32_xm0 = COPY %10.sub1:sreg_128
|
||||
%8:sreg_32_xm0 = COPY %10.sub2:sreg_128
|
||||
%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0, 0
|
||||
%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
|
||||
%8:sreg_32_xm0 = COPY %10.sub2:sgpr_128
|
||||
|
||||
bb.4:
|
||||
S_NOP 0, implicit %10
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# CHECK: S_NOP 0, implicit-def %0
|
||||
# CHECK: S_NOP 0, implicit-def %1
|
||||
# CHECK: S_NOP 0, implicit-def dead %2
|
||||
# CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
|
||||
# CHECK: %3:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub3
|
||||
# CHECK: S_NOP 0, implicit %3.sub0
|
||||
# CHECK: S_NOP 0, implicit %3.sub1
|
||||
# CHECK: S_NOP 0, implicit undef %3.sub2
|
||||
|
|
@ -20,7 +20,7 @@ registers:
|
|||
- { id: 0, class: sreg_32_xm0 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sreg_32_xm0 }
|
||||
- { id: 3, class: sreg_128 }
|
||||
- { id: 3, class: sgpr_128 }
|
||||
- { id: 4, class: sreg_64 }
|
||||
- { id: 5, class: sreg_64 }
|
||||
body: |
|
||||
|
|
@ -42,8 +42,8 @@ body: |
|
|||
# Check defined lanes transfer; Includes checking for some special cases like
|
||||
# undef operands or IMPLICIT_DEF definitions.
|
||||
# CHECK-LABEL: name: test1
|
||||
# CHECK: %0:sreg_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
|
||||
# CHECK: %1:sreg_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
|
||||
# CHECK: %0:sgpr_128 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
|
||||
# CHECK: %1:sgpr_128 = INSERT_SUBREG %0, $sgpr1, %subreg.sub3
|
||||
# CHECK: %2:sreg_64 = INSERT_SUBREG %0.sub2_sub3, $sgpr42, %subreg.sub0
|
||||
# CHECK: S_NOP 0, implicit %1.sub0
|
||||
# CHECK: S_NOP 0, implicit undef %1.sub1
|
||||
|
|
@ -53,7 +53,7 @@ body: |
|
|||
# CHECK: S_NOP 0, implicit undef %2.sub1
|
||||
|
||||
# CHECK: %3:sreg_32_xm0 = IMPLICIT_DEF
|
||||
# CHECK: %4:sreg_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0
|
||||
# CHECK: %4:sgpr_128 = INSERT_SUBREG %0, undef %3, %subreg.sub0
|
||||
# CHECK: S_NOP 0, implicit undef %4.sub0
|
||||
# CHECK: S_NOP 0, implicit undef %4.sub1
|
||||
# CHECK: S_NOP 0, implicit %4.sub2
|
||||
|
|
@ -70,21 +70,21 @@ body: |
|
|||
# CHECK: %9:sreg_32_xm0 = EXTRACT_SUBREG undef %8, %subreg.sub1
|
||||
# CHECK: S_NOP 0, implicit undef %9
|
||||
|
||||
# CHECK: %10:sreg_128 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
|
||||
# CHECK: %10:sgpr_128 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
|
||||
# CHECK: S_NOP 0, implicit undef %10
|
||||
name: test1
|
||||
registers:
|
||||
- { id: 0, class: sreg_128 }
|
||||
- { id: 1, class: sreg_128 }
|
||||
- { id: 0, class: sgpr_128 }
|
||||
- { id: 1, class: sgpr_128 }
|
||||
- { id: 2, class: sreg_64 }
|
||||
- { id: 3, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_128 }
|
||||
- { id: 4, class: sgpr_128 }
|
||||
- { id: 5, class: sreg_64 }
|
||||
- { id: 6, class: sreg_32_xm0 }
|
||||
- { id: 7, class: sreg_32_xm0 }
|
||||
- { id: 8, class: sreg_64 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr0, %subreg.sub2
|
||||
|
|
@ -125,7 +125,7 @@ body: |
|
|||
# CHECK: S_NOP 0, implicit-def dead %0
|
||||
# CHECK: S_NOP 0, implicit-def %1
|
||||
# CHECK: S_NOP 0, implicit-def %2
|
||||
# CHECK: %3:sreg_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
|
||||
# CHECK: %3:sgpr_128 = REG_SEQUENCE undef %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
|
||||
# CHECK: S_NOP 0, implicit %3.sub1
|
||||
# CHECK: S_NOP 0, implicit %3.sub3
|
||||
|
||||
|
|
@ -136,17 +136,17 @@ body: |
|
|||
|
||||
# CHECK: S_NOP 0, implicit-def dead %7
|
||||
# CHECK: S_NOP 0, implicit-def %8
|
||||
# CHECK: %9:sreg_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3
|
||||
# CHECK: %9:sgpr_128 = INSERT_SUBREG undef %7, %8, %subreg.sub2_sub3
|
||||
# CHECK: S_NOP 0, implicit %9.sub2
|
||||
|
||||
# CHECK: S_NOP 0, implicit-def %10
|
||||
# CHECK: S_NOP 0, implicit-def dead %11
|
||||
# CHECK: %12:sreg_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1
|
||||
# CHECK: %12:sgpr_128 = INSERT_SUBREG %10, undef %11, %subreg.sub0_sub1
|
||||
# CHECK: S_NOP 0, implicit %12.sub3
|
||||
|
||||
# CHECK: S_NOP 0, implicit-def %13
|
||||
# CHECK: S_NOP 0, implicit-def dead %14
|
||||
# CHECK: %15:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3
|
||||
# CHECK: %15:sgpr_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, undef %14, %subreg.sub2_sub3
|
||||
# CHECK: %16:sreg_64 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
|
||||
# CHECK: S_NOP 0, implicit %16.sub1
|
||||
|
||||
|
|
@ -155,19 +155,19 @@ registers:
|
|||
- { id: 0, class: sreg_32_xm0 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sreg_64 }
|
||||
- { id: 3, class: sreg_128 }
|
||||
- { id: 3, class: sgpr_128 }
|
||||
- { id: 4, class: sreg_32_xm0 }
|
||||
- { id: 5, class: sreg_32_xm0 }
|
||||
- { id: 6, class: sreg_64 }
|
||||
- { id: 7, class: sreg_128 }
|
||||
- { id: 7, class: sgpr_128 }
|
||||
- { id: 8, class: sreg_64 }
|
||||
- { id: 9, class: sreg_128 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 9, class: sgpr_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: sreg_64 }
|
||||
- { id: 12, class: sreg_128 }
|
||||
- { id: 12, class: sgpr_128 }
|
||||
- { id: 13, class: sreg_64 }
|
||||
- { id: 14, class: sreg_64 }
|
||||
- { id: 15, class: sreg_128 }
|
||||
- { id: 15, class: sgpr_128 }
|
||||
- { id: 16, class: sreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
|
|
@ -265,10 +265,10 @@ body: |
|
|||
# CHECK: S_NOP 0, implicit-def %0
|
||||
# CHECK: S_NOP 0, implicit-def dead %1
|
||||
# CHECK: S_NOP 0, implicit-def dead %2
|
||||
# CHECK: %3:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, undef %1, %subreg.sub1, undef %2, %subreg.sub2
|
||||
# CHECK: %3:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, undef %1, %subreg.sub1, undef %2, %subreg.sub2
|
||||
|
||||
# CHECK: bb.1:
|
||||
# CHECK: %4:sreg_128 = PHI %3, %bb.0, %5, %bb.1
|
||||
# CHECK: %4:sgpr_128 = PHI %3, %bb.0, %5, %bb.1
|
||||
|
||||
# CHECK: bb.2:
|
||||
# CHECK: S_NOP 0, implicit %4.sub0
|
||||
|
|
@ -279,9 +279,9 @@ registers:
|
|||
- { id: 0, class: sreg_32_xm0 }
|
||||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sreg_32_xm0 }
|
||||
- { id: 3, class: sreg_128 }
|
||||
- { id: 4, class: sreg_128 }
|
||||
- { id: 5, class: sreg_128 }
|
||||
- { id: 3, class: sgpr_128 }
|
||||
- { id: 4, class: sgpr_128 }
|
||||
- { id: 5, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def %0
|
||||
|
|
@ -315,12 +315,12 @@ body: |
|
|||
# CHECK: S_NOP 0, implicit-def %1
|
||||
# CHECK: S_NOP 0, implicit-def dead %2
|
||||
# CHECK: S_NOP 0, implicit-def %3
|
||||
# CHECK: %4:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub2, %3, %subreg.sub3
|
||||
# CHECK: %4:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, undef %2, %subreg.sub2, %3, %subreg.sub3
|
||||
|
||||
# CHECK: bb.1:
|
||||
# CHECK: %5:sreg_128 = PHI %4, %bb.0, %6, %bb.1
|
||||
# CHECK: %5:sgpr_128 = PHI %4, %bb.0, %6, %bb.1
|
||||
|
||||
# CHECK: %6:sreg_128 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, undef %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
|
||||
# CHECK: %6:sgpr_128 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, undef %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
|
||||
|
||||
# CHECK: bb.2:
|
||||
# CHECK: S_NOP 0, implicit %6.sub3
|
||||
|
|
@ -331,9 +331,9 @@ registers:
|
|||
- { id: 1, class: sreg_32_xm0 }
|
||||
- { id: 2, class: sreg_32_xm0 }
|
||||
- { id: 3, class: sreg_32_xm0 }
|
||||
- { id: 4, class: sreg_128 }
|
||||
- { id: 5, class: sreg_128 }
|
||||
- { id: 6, class: sreg_128 }
|
||||
- { id: 4, class: sgpr_128 }
|
||||
- { id: 5, class: sgpr_128 }
|
||||
- { id: 6, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def %0
|
||||
|
|
@ -361,12 +361,12 @@ body: |
|
|||
# CHECK-LABEL: name: loop2
|
||||
# CHECK: bb.0:
|
||||
# CHECK: S_NOP 0, implicit-def %0
|
||||
# CHECK: %1:sreg_128 = REG_SEQUENCE %0, %subreg.sub0
|
||||
# CHECK: %1:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0
|
||||
|
||||
# CHECK: bb.1:
|
||||
# CHECK: %2:sreg_128 = PHI %1, %bb.0, %3, %bb.1
|
||||
# CHECK: %2:sgpr_128 = PHI %1, %bb.0, %3, %bb.1
|
||||
|
||||
# CHECK: %3:sreg_128 = REG_SEQUENCE %2.sub3, %subreg.sub0, undef %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
|
||||
# CHECK: %3:sgpr_128 = REG_SEQUENCE %2.sub3, %subreg.sub0, undef %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
|
||||
|
||||
# CHECK: bb.2:
|
||||
# CHECK: S_NOP 0, implicit %2.sub0
|
||||
|
|
@ -377,9 +377,9 @@ name: loop2
|
|||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sreg_32_xm0 }
|
||||
- { id: 1, class: sreg_128 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 3, class: sreg_128 }
|
||||
- { id: 1, class: sgpr_128 }
|
||||
- { id: 2, class: sgpr_128 }
|
||||
- { id: 3, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def %0
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ define amdgpu_hs void @main([0 x i8] addrspace(6)* inreg %arg) {
|
|||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
|
||||
; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
|
||||
; GCN: [[DEF1:%[0-9]+]]:sreg_128 = IMPLICIT_DEF
|
||||
; GCN: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
|
||||
; GCN: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[DEF1]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from custom TargetCustom7, align 1, addrspace 4)
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
|
||||
|
|
@ -20,7 +20,7 @@ define amdgpu_hs void @main([0 x i8] addrspace(6)* inreg %arg) {
|
|||
; GCN: [[COPY4:%[0-9]+]]:vreg_96 = COPY [[REG_SEQUENCE]]
|
||||
; GCN: [[DEF2:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
|
||||
; GCN: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
|
||||
; GCN: [[DEF3:%[0-9]+]]:sreg_128 = IMPLICIT_DEF
|
||||
; GCN: [[DEF3:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
|
||||
; GCN: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4)
|
||||
; GCN: S_ENDPGM 0
|
||||
main_body:
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ body: |
|
|||
liveins: $vgpr0, $sgpr0_sgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%2:sreg_128 = S_LOAD_DWORDX4_IMM %1, 9, 0, 0
|
||||
%2:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 9, 0, 0
|
||||
%3:sreg_32_xm0 = S_MOV_B32 2
|
||||
%4:vgpr_32 = V_LSHLREV_B32_e64 killed %3, %0, implicit $exec
|
||||
%5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -193,7 +193,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -259,7 +259,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -329,7 +329,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -398,7 +398,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -463,7 +463,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -535,7 +535,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -602,7 +602,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
@ -668,7 +668,7 @@ registers:
|
|||
- { id: 7, class: sreg_32 }
|
||||
- { id: 8, class: sreg_32 }
|
||||
- { id: 9, class: sreg_32 }
|
||||
- { id: 10, class: sreg_128 }
|
||||
- { id: 10, class: sgpr_128 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ registers:
|
|||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: sreg_32 }
|
||||
- { id: 4, class: vgpr_32 }
|
||||
- { id: 5, class: sreg_128 }
|
||||
- { id: 5, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0 (%ir-block.0):
|
||||
%0 = IMPLICIT_DEF
|
||||
|
|
|
|||
|
|
@ -238,7 +238,7 @@ body: |
|
|||
GLOBAL_STORE_DWORDX2 %11, %77, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
GLOBAL_ATOMIC_UMAX_X2 %11, %16, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
|
||||
|
||||
%79:sreg_128 = REG_SEQUENCE %4, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3
|
||||
%79:sgpr_128 = REG_SEQUENCE %4, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3
|
||||
%80:vreg_128 = COPY %79
|
||||
|
||||
%78:vreg_64 = GLOBAL_ATOMIC_CMPSWAP_X2_RTN %11, %80, 16, 0, implicit $exec :: (volatile load store seq_cst 4, addrspace 1)
|
||||
|
|
|
|||
|
|
@ -304,10 +304,10 @@ body: |
|
|||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: image_clause{{$}}
|
||||
# GCN: early-clobber %4:vreg_128, early-clobber %3:vreg_128, early-clobber %5:vreg_128 = BUNDLE %0, undef %2:sreg_128, %1, implicit $exec {
|
||||
# GCN-NEXT: %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN: early-clobber %4:vreg_128, early-clobber %3:vreg_128, early-clobber %5:vreg_128 = BUNDLE %0, undef %2:sgpr_128, %1, implicit $exec {
|
||||
# GCN-NEXT: %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
|
||||
|
|
@ -317,7 +317,7 @@ tracksRegLiveness: true
|
|||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: sreg_256 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 2, class: sgpr_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
- { id: 5, class: vreg_128 }
|
||||
|
|
@ -325,9 +325,9 @@ body: |
|
|||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %4, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %5, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
|
|
@ -346,7 +346,7 @@ tracksRegLiveness: true
|
|||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: sreg_256 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 2, class: sgpr_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
|
|
|
|||
|
|
@ -154,7 +154,7 @@ body: |
|
|||
%6:sreg_32_xm0_xexec = S_MOV_B32 0
|
||||
%7:sreg_32_xm0 = S_MOV_B32 0
|
||||
%8:sreg_64_xexec = REG_SEQUENCE killed %6, %subreg.sub0, %7, %subreg.sub1
|
||||
%9:sreg_128 = S_LOAD_DWORDX4_IMM killed %8, 0, 0, 0 :: (invariant load 16, addrspace 6)
|
||||
%9:sgpr_128 = S_LOAD_DWORDX4_IMM killed %8, 0, 0, 0 :: (invariant load 16, addrspace 6)
|
||||
%31:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_IMM %9, 0, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%10:sreg_32_xm0_xexec = COPY %31.sub0
|
||||
%11:sreg_32_xm0_xexec = COPY killed %31.sub1
|
||||
|
|
@ -179,7 +179,7 @@ body: |
|
|||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
|
||||
%0:sreg_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %0, 0, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%2:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM %0, 1, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%3:vgpr_32 = BUFFER_LOAD_DWORD_OFFSET %0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
# W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -42,7 +42,7 @@
|
|||
# W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W32: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -71,7 +71,7 @@ body: |
|
|||
%2:vgpr_32 = COPY $vgpr2
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
$sgpr30_sgpr31 = COPY %5
|
||||
$vgpr0 = COPY %7
|
||||
|
|
@ -89,7 +89,7 @@ body: |
|
|||
# W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -111,7 +111,7 @@ body: |
|
|||
# W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W32: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -140,7 +140,7 @@ body: |
|
|||
%2:vgpr_32 = COPY $vgpr2
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
$sgpr30_sgpr31 = COPY %5
|
||||
$vgpr0 = COPY %7
|
||||
|
|
@ -158,7 +158,7 @@ body: |
|
|||
# W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -180,7 +180,7 @@ body: |
|
|||
# W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W32: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -209,7 +209,7 @@ body: |
|
|||
%2:vgpr_32 = COPY $vgpr2
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
$sgpr30_sgpr31 = COPY %5
|
||||
$vgpr0 = COPY %7
|
||||
|
|
@ -222,7 +222,7 @@ body: |
|
|||
# ADDR64: %15:sreg_64 = S_MOV_B64 0
|
||||
# ADDR64: %16:sgpr_32 = S_MOV_B32 0
|
||||
# ADDR64: %17:sgpr_32 = S_MOV_B32 61440
|
||||
# ADDR64: %18:sreg_128 = REG_SEQUENCE %15, %subreg.sub0_sub1, %16, %subreg.sub2, %17, %subreg.sub3
|
||||
# ADDR64: %18:sgpr_128 = REG_SEQUENCE %15, %subreg.sub0_sub1, %16, %subreg.sub2, %17, %subreg.sub3
|
||||
# ADDR64: %9:vgpr_32, %12:sreg_64_xexec = V_ADD_I32_e64 %14.sub0, %4.sub0, 0, implicit $exec
|
||||
# ADDR64: %10:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %14.sub1, %4.sub1, killed %12, 0, implicit $exec
|
||||
# ADDR64: %11:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %10, %subreg.sub1
|
||||
|
|
@ -245,7 +245,7 @@ body: |
|
|||
%2:vgpr_32 = COPY $vgpr2
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %4, killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
$sgpr30_sgpr31 = COPY %5
|
||||
$vgpr0 = COPY %7
|
||||
|
|
@ -264,7 +264,7 @@ body: |
|
|||
# W64-NO-ADDR64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W64-NO-ADDR64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W64-NO-ADDR64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W64-NO-ADDR64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64-NO-ADDR64: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W64-NO-ADDR64: [[CMP0:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W64-NO-ADDR64: [[CMP1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W64-NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -284,7 +284,7 @@ body: |
|
|||
# W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
|
||||
# W32: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
|
||||
# W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
|
||||
# W32: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[SRSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
|
||||
# W32: [[CMP0:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
|
||||
# W32: [[CMP1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
|
||||
# W32: [[CMP:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[CMP0]], [[CMP1]], implicit-def $scc
|
||||
|
|
@ -301,7 +301,7 @@ body: |
|
|||
# ADDR64: [[ZERO64:%[0-9]+]]:sreg_64 = S_MOV_B64 0
|
||||
# ADDR64: [[RSRCFMTLO:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
|
||||
# ADDR64: [[RSRCFMTHI:%[0-9]+]]:sgpr_32 = S_MOV_B32 61440
|
||||
# ADDR64: [[ZERORSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3
|
||||
# ADDR64: [[ZERORSRC:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3
|
||||
# ADDR64: [[VADDR64:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[RSRCPTR]].sub0, %subreg.sub0, [[RSRCPTR]].sub1, %subreg.sub1
|
||||
# ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 [[VADDR64]], [[ZERORSRC]], 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
|
||||
|
|
@ -323,7 +323,7 @@ body: |
|
|||
%2:vgpr_32 = COPY $vgpr2
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
|
||||
%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed %6, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
$sgpr30_sgpr31 = COPY %5
|
||||
$vgpr0 = COPY %7
|
||||
|
|
|
|||
|
|
@ -465,17 +465,17 @@ body: |
|
|||
...
|
||||
|
||||
# GCN: name: negated_cond_subreg
|
||||
# GCN: %0.sub0_sub1:sreg_128 = IMPLICIT_DEF
|
||||
# GCN: %0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
|
||||
# GCN-NEXT: $vcc = S_ANDN2_B64 $exec, %0.sub0_sub1, implicit-def $scc
|
||||
# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc
|
||||
---
|
||||
name: negated_cond_subreg
|
||||
body: |
|
||||
bb.0:
|
||||
%0.sub0_sub1:sreg_128 = IMPLICIT_DEF
|
||||
%0.sub0_sub1:sgpr_128 = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0.sub0_sub1, implicit $exec
|
||||
%2.sub0_sub1:sreg_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
||||
$vcc = S_AND_B64 $exec, killed %2.sub0_sub1:sreg_128, implicit-def dead $scc
|
||||
%2.sub0_sub1:sgpr_128 = V_CMP_NE_U32_e64 %1, 1, implicit $exec
|
||||
$vcc = S_AND_B64 $exec, killed %2.sub0_sub1:sgpr_128, implicit-def dead $scc
|
||||
S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc
|
||||
S_BRANCH %bb.1
|
||||
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ body: |
|
|||
%4:vgpr_32 = PHI %19, %bb.3, %3, %bb.2, %18, %bb.0
|
||||
%15:sreg_32_xm0 = S_MOV_B32 61440
|
||||
%16:sreg_32_xm0 = S_MOV_B32 -1
|
||||
%17:sreg_128 = REG_SEQUENCE undef %14:sreg_32_xm0, %subreg.sub0, undef %12:sreg_32_xm0, %subreg.sub1, %16, %subreg.sub2, %15, %subreg.sub3
|
||||
%17:sgpr_128 = REG_SEQUENCE undef %14:sreg_32_xm0, %subreg.sub0, undef %12:sreg_32_xm0, %subreg.sub1, %16, %subreg.sub2, %15, %subreg.sub3
|
||||
BUFFER_STORE_DWORD_OFFSET %4, %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
%19:vgpr_32 = COPY %4
|
||||
%20:sreg_64 = SI_IF %0, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ body: |
|
|||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sgpr_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%4:sreg_32_xm0 = COPY $sgpr101
|
||||
%5:sreg_32_xm0 = S_MOV_B32 0
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
|
|
@ -62,7 +62,7 @@ body: |
|
|||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sgpr_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%4:sreg_32_xm0 = COPY $sgpr101
|
||||
%5:sreg_32_xm0 = S_MOV_B32 0
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
|
|
@ -115,7 +115,7 @@ body: |
|
|||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sgpr_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%4:sreg_32_xm0 = COPY $sgpr101
|
||||
%5:sreg_32_xm0 = S_MOV_B32 0
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
|
|
@ -160,7 +160,7 @@ body: |
|
|||
bb.0.entry:
|
||||
%0:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0, 36, 0, 0
|
||||
%3:sreg_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%3:sgpr_128 = COPY $sgpr96_sgpr97_sgpr98_sgpr99
|
||||
%4:sreg_32_xm0 = COPY $sgpr101
|
||||
%5:sreg_32_xm0 = S_MOV_B32 0
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
|
|
|
|||
|
|
@ -325,7 +325,7 @@ body: |
|
|||
name: smem_bundle
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sreg_128, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3' }
|
||||
- { id: 0, class: sgpr_128, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3' }
|
||||
- { id: 1, class: sreg_32_xm0_xexec, preferred-register: '$sgpr16' }
|
||||
- { id: 2, class: sreg_32_xm0_xexec, preferred-register: '$sgpr17' }
|
||||
- { id: 3, class: sreg_32_xm0_xexec, preferred-register: '$sgpr4' }
|
||||
|
|
|
|||
|
|
@ -15,36 +15,36 @@
|
|||
name: regcoal-subrange-join-seg
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sreg_128 }
|
||||
- { id: 1, class: sreg_128 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 3, class: sreg_128 }
|
||||
- { id: 4, class: sreg_128 }
|
||||
- { id: 5, class: sreg_128 }
|
||||
- { id: 6, class: sreg_128 }
|
||||
- { id: 7, class: sreg_128 }
|
||||
- { id: 8, class: sreg_128 }
|
||||
- { id: 0, class: sgpr_128 }
|
||||
- { id: 1, class: sgpr_128 }
|
||||
- { id: 2, class: sgpr_128 }
|
||||
- { id: 3, class: sgpr_128 }
|
||||
- { id: 4, class: sgpr_128 }
|
||||
- { id: 5, class: sgpr_128 }
|
||||
- { id: 6, class: sgpr_128 }
|
||||
- { id: 7, class: sgpr_128 }
|
||||
- { id: 8, class: sgpr_128 }
|
||||
- { id: 9, class: sreg_32_xm0 }
|
||||
- { id: 10, class: sreg_32_xm0 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
- { id: 14, class: sreg_32_xm0_xexec }
|
||||
- { id: 15, class: sreg_128 }
|
||||
- { id: 15, class: sgpr_128 }
|
||||
- { id: 16, class: sreg_32 }
|
||||
- { id: 17, class: sreg_32_xm0 }
|
||||
- { id: 18, class: sreg_32_xm0 }
|
||||
- { id: 19, class: sreg_32_xm0 }
|
||||
- { id: 20, class: sreg_32_xm0 }
|
||||
- { id: 21, class: sreg_32_xm0_xexec }
|
||||
- { id: 22, class: sreg_128 }
|
||||
- { id: 22, class: sgpr_128 }
|
||||
- { id: 23, class: sreg_32_xm0 }
|
||||
- { id: 24, class: vgpr_32 }
|
||||
- { id: 25, class: sreg_64_xexec }
|
||||
- { id: 26, class: vgpr_32 }
|
||||
- { id: 27, class: sreg_32_xm0 }
|
||||
- { id: 28, class: sreg_32 }
|
||||
- { id: 29, class: sreg_128 }
|
||||
- { id: 29, class: sgpr_128 }
|
||||
- { id: 30, class: sreg_32_xm0 }
|
||||
- { id: 31, class: sreg_32_xm0 }
|
||||
- { id: 32, class: vgpr_32 }
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ registers:
|
|||
- { id: 22, class: sreg_32_xm0_xexec }
|
||||
- { id: 23, class: sreg_32_xm0 }
|
||||
- { id: 24, class: sreg_64_xexec }
|
||||
- { id: 25, class: sreg_128 }
|
||||
- { id: 25, class: sgpr_128 }
|
||||
- { id: 26, class: sreg_64_xexec }
|
||||
- { id: 27, class: sreg_32_xm0_xexec }
|
||||
- { id: 28, class: sreg_32_xm0 }
|
||||
|
|
@ -57,7 +57,7 @@ registers:
|
|||
- { id: 35, class: vgpr_32 }
|
||||
- { id: 36, class: vgpr_32 }
|
||||
- { id: 37, class: vgpr_32 }
|
||||
- { id: 38, class: sreg_128 }
|
||||
- { id: 38, class: sgpr_128 }
|
||||
- { id: 39, class: sreg_64_xexec }
|
||||
- { id: 40, class: sreg_32_xm0_xexec }
|
||||
- { id: 41, class: sreg_32_xm0 }
|
||||
|
|
@ -70,7 +70,7 @@ registers:
|
|||
- { id: 48, class: vgpr_32 }
|
||||
- { id: 49, class: vgpr_32 }
|
||||
- { id: 50, class: vgpr_32 }
|
||||
- { id: 51, class: sreg_128 }
|
||||
- { id: 51, class: sgpr_128 }
|
||||
- { id: 52, class: vgpr_32 }
|
||||
- { id: 53, class: vgpr_32 }
|
||||
- { id: 54, class: vgpr_32 }
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ body: |
|
|||
%23:vgpr_32 = V_CVT_U32_F32_e32 killed %21, implicit $exec
|
||||
%108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
|
||||
undef %109.sub1:vreg_128 = COPY %108
|
||||
%28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sreg_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sgpr_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
|
||||
S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC0 %bb.2, implicit killed $scc
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ body: |
|
|||
S_BRANCH %bb.6
|
||||
|
||||
bb.6:
|
||||
%36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sreg_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sgpr_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%39:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
|
||||
%40:vgpr_32 = V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
|
||||
%41:vgpr_32 = V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $exec
|
||||
|
|
@ -83,7 +83,7 @@ body: |
|
|||
S_BRANCH %bb.8
|
||||
|
||||
bb.8:
|
||||
dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sreg_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
|
||||
dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sgpr_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
|
||||
%138:vreg_128 = COPY killed %111
|
||||
|
||||
bb.9:
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
# CHECK: S_NOP 0, implicit %0
|
||||
name: test0
|
||||
registers:
|
||||
- { id: 0, class: sreg_128 }
|
||||
- { id: 0, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def undef %0.sub0
|
||||
|
|
@ -46,8 +46,8 @@ body: |
|
|||
# CHECK: S_NOP 0, implicit %2.sub
|
||||
name: test1
|
||||
registers:
|
||||
- { id: 0, class: sreg_128 }
|
||||
- { id: 1, class: sreg_128 }
|
||||
- { id: 0, class: sgpr_128 }
|
||||
- { id: 1, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def undef %0.sub2
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ regBankSelected: false
|
|||
selected: false
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: sreg_128 }
|
||||
- { id: 0, class: sgpr_128 }
|
||||
- { id: 1, class: sgpr_64 }
|
||||
- { id: 2, class: sreg_32_xm0 }
|
||||
- { id: 3, class: sgpr_32 }
|
||||
|
|
|
|||
|
|
@ -14,28 +14,28 @@ machineFunctionInfo:
|
|||
stackPtrOffsetReg: $sgpr32
|
||||
registers:
|
||||
- { id: 0, class: sreg_64 }
|
||||
- { id: 1100, class: sreg_128 }
|
||||
- { id: 1101, class: sreg_128 }
|
||||
- { id: 1102, class: sreg_128 }
|
||||
- { id: 1103, class: sreg_128 }
|
||||
- { id: 1104, class: sreg_128 }
|
||||
- { id: 1105, class: sreg_128 }
|
||||
- { id: 1106, class: sreg_128 }
|
||||
- { id: 1107, class: sreg_128 }
|
||||
- { id: 1108, class: sreg_128 }
|
||||
- { id: 1109, class: sreg_128 }
|
||||
- { id: 1110, class: sreg_128 }
|
||||
- { id: 1111, class: sreg_128 }
|
||||
- { id: 1112, class: sreg_128 }
|
||||
- { id: 1113, class: sreg_128 }
|
||||
- { id: 1114, class: sreg_128 }
|
||||
- { id: 1115, class: sreg_128 }
|
||||
- { id: 1116, class: sreg_128 }
|
||||
- { id: 1117, class: sreg_128 }
|
||||
- { id: 1118, class: sreg_128 }
|
||||
- { id: 1119, class: sreg_128 }
|
||||
- { id: 1120, class: sreg_128 }
|
||||
- { id: 1121, class: sreg_128 }
|
||||
- { id: 1100, class: sgpr_128 }
|
||||
- { id: 1101, class: sgpr_128 }
|
||||
- { id: 1102, class: sgpr_128 }
|
||||
- { id: 1103, class: sgpr_128 }
|
||||
- { id: 1104, class: sgpr_128 }
|
||||
- { id: 1105, class: sgpr_128 }
|
||||
- { id: 1106, class: sgpr_128 }
|
||||
- { id: 1107, class: sgpr_128 }
|
||||
- { id: 1108, class: sgpr_128 }
|
||||
- { id: 1109, class: sgpr_128 }
|
||||
- { id: 1110, class: sgpr_128 }
|
||||
- { id: 1111, class: sgpr_128 }
|
||||
- { id: 1112, class: sgpr_128 }
|
||||
- { id: 1113, class: sgpr_128 }
|
||||
- { id: 1114, class: sgpr_128 }
|
||||
- { id: 1115, class: sgpr_128 }
|
||||
- { id: 1116, class: sgpr_128 }
|
||||
- { id: 1117, class: sgpr_128 }
|
||||
- { id: 1118, class: sgpr_128 }
|
||||
- { id: 1119, class: sgpr_128 }
|
||||
- { id: 1120, class: sgpr_128 }
|
||||
- { id: 1121, class: sgpr_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
|
|
|
|||
|
|
@ -18,8 +18,8 @@
|
|||
name: func0
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sreg_128
|
||||
S_NOP 0, implicit-def %0.sub3 : sreg_128
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sgpr_128
|
||||
S_NOP 0, implicit-def %0.sub3 : sgpr_128
|
||||
|
||||
; Clobber registers
|
||||
S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1, implicit-def dead $sgpr2, implicit-def dead $sgpr3, implicit-def dead $sgpr4, implicit-def dead $sgpr5, implicit-def dead $sgpr6, implicit-def dead $sgpr7, implicit-def dead $sgpr8, implicit-def dead $sgpr9, implicit-def dead $sgpr10, implicit-def dead $sgpr11
|
||||
|
|
@ -49,7 +49,7 @@ tracksRegLiveness: true
|
|||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1, $sgpr2
|
||||
undef %0.sub0 : sreg_128 = COPY $sgpr0
|
||||
undef %0.sub0 : sgpr_128 = COPY $sgpr0
|
||||
%0.sub2 = COPY $sgpr2
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||||
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||||
S_NOP 0, implicit-def dead $sgpr0, implicit-def dead $sgpr1
|
||||
|
|
@ -75,8 +75,8 @@ tracksRegLiveness: true
|
|||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sreg_128
|
||||
S_NOP 0, implicit-def %0.sub3 : sreg_128
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sgpr_128
|
||||
S_NOP 0, implicit-def %0.sub3 : sgpr_128
|
||||
|
||||
S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
|
||||
S_BRANCH %bb.2
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ body: |
|
|||
%11.sub5:sreg_256 = COPY %11.sub0
|
||||
%11.sub6:sreg_256 = COPY %11.sub0
|
||||
%11.sub7:sreg_256 = COPY %11.sub0
|
||||
%12:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %9, %11, undef %13:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%12:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %9, %11, undef %13:sgpr_128, 15, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
|
||||
%14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
|
||||
%15:vreg_128 = IMPLICIT_DEF
|
||||
S_CBRANCH_SCC1 %bb.8, implicit undef $scc
|
||||
|
|
@ -164,12 +164,12 @@ body: |
|
|||
|
||||
%18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $exec
|
||||
%19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
|
||||
%20:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sreg_128, 1040, 0, 0 :: (dereferenceable invariant load 16)
|
||||
%20:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sgpr_128, 1040, 0, 0 :: (dereferenceable invariant load 16)
|
||||
%22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $exec
|
||||
%23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%24:vgpr_32 = COPY %20.sub3
|
||||
%25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $exec
|
||||
%26:sreg_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sreg_128, 1056, 0, 0 :: (dereferenceable invariant load 16)
|
||||
%26:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sgpr_128, 1056, 0, 0 :: (dereferenceable invariant load 16)
|
||||
%28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $exec
|
||||
%29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $exec
|
||||
%30:vgpr_32 = V_RCP_F32_e32 %29, implicit $exec
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
name: func0
|
||||
body: |
|
||||
bb.0:
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sreg_128
|
||||
S_NOP 0, implicit-def undef %0.sub0 : sgpr_128
|
||||
S_NOP 0, implicit-def %0.sub3
|
||||
S_NOP 0, implicit-def undef %1.sub1 : sreg_128
|
||||
S_NOP 0, implicit-def undef %1.sub1 : sgpr_128
|
||||
S_NOP 0, implicit-def %1.sub2
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ body: |
|
|||
successors: %bb.1, %bb.2
|
||||
|
||||
%1:sgpr_64 = COPY $sgpr0_sgpr1
|
||||
%4:sreg_128 = S_LOAD_DWORDX4_IMM %1, 36, 0, 0
|
||||
%4:sgpr_128 = S_LOAD_DWORDX4_IMM %1, 36, 0, 0
|
||||
%11:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4.sub2_sub3, 0, 0, 0
|
||||
undef %15.sub0:vreg_64 = COPY %4.sub0
|
||||
%15.sub1:vreg_64 = COPY %4.sub1
|
||||
|
|
|
|||
Loading…
Reference in New Issue