forked from OSchip/llvm-project
[AArch64][SVE] Asm: Support for FP Complex ADD/MLA.
The variants added in this patch are: - Predicated Complex floating point ADD with rotate, e.g. fcadd z0.h, p0/m, z0.h, z1.h, #90 - Predicated Complex floating point MLA with rotate, e.g. fcmla z0.h, p0/m, z1.h, z2.h, #180 - Unpredicated Complex floating point MLA with rotate (indexed operand), e.g. fcmla z0.h, p0/m, z1.h, z2.h[0], #180 Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D48824 llvm-svn: 336210
This commit is contained in:
Sander de Smalen
parent
d912ffaba5
commit
128fdfa23f
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@ -56,7 +56,10 @@ let Predicates = [HasSVE] in {
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defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
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defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
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defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
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defm FCMLA_ZPmZZ : sve_fp_fcmla<"fcmla">;
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defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla">;
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defm FMUL_ZZZI : sve_fp_fmul_by_indexed_elem<"fmul">;
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// Splat immediate (unpredicated)
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@ -1044,14 +1044,16 @@ public:
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}
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template<int64_t Angle, int64_t Remainder>
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bool isComplexRotation() const {
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if (!isImm()) return false;
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DiagnosticPredicate isComplexRotation() const {
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if (!isImm()) return DiagnosticPredicateTy::NoMatch;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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if (!CE) return DiagnosticPredicateTy::NoMatch;
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uint64_t Value = CE->getValue();
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return (Value % Angle == Remainder && Value <= 270);
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if (Value % Angle == Remainder && Value <= 270)
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return DiagnosticPredicateTy::Match;
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return DiagnosticPredicateTy::NearMatch;
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}
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template <unsigned RegClassID> bool isGPR64() const {
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@ -821,6 +821,111 @@ multiclass sve_fp_fmul_by_indexed_elem<string asm> {
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}
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Multiply-Add Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
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complexrotateop:$imm),
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asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
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"", []>, Sched<[]> {
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bits<5> Zda;
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bits<3> Pg;
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bits<5> Zn;
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bits<5> Zm;
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bits<2> imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21} = 0;
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let Inst{20-16} = Zm;
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let Inst{15} = 0;
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let Inst{14-13} = imm;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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}
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multiclass sve_fp_fcmla<string asm> {
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def _H : sve_fp_fcmla<0b01, asm, ZPR16>;
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def _S : sve_fp_fcmla<0b10, asm, ZPR32>;
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def _D : sve_fp_fcmla<0b11, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Multiply-Add - Indexed Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm,
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ZPRRegOp zprty,
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ZPRRegOp zprty2, Operand itype>
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: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
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complexrotateop:$imm),
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asm, "\t$Zda, $Zn, $Zm$iop, $imm",
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"", []>, Sched<[]> {
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bits<5> Zda;
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bits<5> Zn;
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bits<2> imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21} = 0b1;
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let Inst{15-12} = 0b0001;
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let Inst{11-10} = imm;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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}
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multiclass sve_fp_fcmla_by_indexed_elem<string asm> {
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def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> {
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bits<3> Zm;
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bits<2> iop;
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let Inst{20-19} = iop;
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let Inst{18-16} = Zm;
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}
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def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> {
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bits<4> Zm;
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bits<1> iop;
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let Inst{20} = iop;
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let Inst{19-16} = Zm;
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}
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Addition Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
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complexrotateopodd:$imm),
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asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
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"",
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[]>, Sched<[]> {
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bits<5> Zdn;
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bits<5> Zm;
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bits<3> Pg;
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bit imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21-17} = 0;
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let Inst{16} = imm;
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let Inst{15-13} = 0b100;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_fp_fcadd<string asm> {
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def _H : sve_fp_fcadd<0b01, asm, ZPR16>;
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def _S : sve_fp_fcadd<0b10, asm, ZPR32>;
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def _D : sve_fp_fcadd<0b11, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Stack Allocation Group
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//===----------------------------------------------------------------------===//
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@ -0,0 +1,37 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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fcadd z0.d, p2/m, z1.d, z2.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: fcadd z0.d, p2/m, z1.d, z2.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Restricted predicate out of range.
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fcadd z0.d, p8/m, z0.d, z1.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fcadd z0.d, p8/m, z0.d, z1.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid rotation
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fcadd z0.d, p0/m, z0.d, z1.d, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcadd z0.d, p0/m, z0.d, z1.d, #180
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #180
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcadd z0.d, p0/m, z0.d, z1.d, #450
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #450
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,44 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fcadd z0.h, p0/m, z0.h, z0.h, #90
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// CHECK-INST: fcadd z0.h, p0/m, z0.h, z0.h, #90
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// CHECK-ENCODING: [0x00,0x80,0x40,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 40 64 <unknown>
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fcadd z0.s, p0/m, z0.s, z0.s, #90
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// CHECK-INST: fcadd z0.s, p0/m, z0.s, z0.s, #90
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// CHECK-ENCODING: [0x00,0x80,0x80,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 80 64 <unknown>
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fcadd z0.d, p0/m, z0.d, z0.d, #90
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// CHECK-INST: fcadd z0.d, p0/m, z0.d, z0.d, #90
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// CHECK-ENCODING: [0x00,0x80,0xc0,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 80 c0 64 <unknown>
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fcadd z31.h, p7/m, z31.h, z31.h, #270
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// CHECK-INST: fcadd z31.h, p7/m, z31.h, z31.h, #270
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// CHECK-ENCODING: [0xff,0x9f,0x41,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 9f 41 64 <unknown>
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fcadd z31.s, p7/m, z31.s, z31.s, #270
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// CHECK-INST: fcadd z31.s, p7/m, z31.s, z31.s, #270
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// CHECK-ENCODING: [0xff,0x9f,0x81,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 9f 81 64 <unknown>
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fcadd z31.d, p7/m, z31.d, z31.d, #270
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// CHECK-INST: fcadd z31.d, p7/m, z31.d, z31.d, #270
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// CHECK-ENCODING: [0xff,0x9f,0xc1,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 9f c1 64 <unknown>
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@ -0,0 +1,52 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Restricted predicate out of range.
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fcmla z0.d, p8/m, z1.d, z2.d, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: fcmla z0.d, p8/m, z1.d, z2.d, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid rotation
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fcmla z0.d, p0/m, z1.d, z2.d, #360
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
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// CHECK-NEXT: fcmla z0.d, p0/m, z1.d, z2.d, #360
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcmla z0.d, p0/m, z1.d, z2.d, #450
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 0, 90, 180 or 270.
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// CHECK-NEXT: fcmla z0.d, p0/m, z1.d, z2.d, #450
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Index out of bounds or invalid for element size
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fcmla z0.h, z1.h, z2.h[-1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: fcmla z0.h, z1.h, z2.h[-1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcmla z0.h, z1.h, z2.h[4], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: fcmla z0.h, z1.h, z2.h[4], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcmla z0.s, z1.s, z2.s[-1], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: fcmla z0.s, z1.s, z2.s[-1], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcmla z0.s, z1.s, z2.s[2], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: fcmla z0.s, z1.s, z2.s[2], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcmla z0.d, z1.d, z2.d[0], #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: fcmla z0.d, z1.d, z2.d[0], #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,104 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fcmla z0.h, p0/m, z0.h, z0.h, #0
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// CHECK-INST: fcmla z0.h, p0/m, z0.h, z0.h, #0
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// CHECK-ENCODING: [0x00,0x00,0x40,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 00 40 64 <unknown>
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fcmla z0.s, p0/m, z0.s, z0.s, #0
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// CHECK-INST: fcmla z0.s, p0/m, z0.s, z0.s, #0
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// CHECK-ENCODING: [0x00,0x00,0x80,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 00 80 64 <unknown>
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fcmla z0.d, p0/m, z0.d, z0.d, #0
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// CHECK-INST: fcmla z0.d, p0/m, z0.d, z0.d, #0
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// CHECK-ENCODING: [0x00,0x00,0xc0,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 00 c0 64 <unknown>
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fcmla z0.h, p0/m, z1.h, z2.h, #90
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// CHECK-INST: fcmla z0.h, p0/m, z1.h, z2.h, #90
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// CHECK-ENCODING: [0x20,0x20,0x42,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 20 42 64 <unknown>
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fcmla z0.s, p0/m, z1.s, z2.s, #90
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// CHECK-INST: fcmla z0.s, p0/m, z1.s, z2.s, #90
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// CHECK-ENCODING: [0x20,0x20,0x82,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 20 82 64 <unknown>
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fcmla z0.d, p0/m, z1.d, z2.d, #90
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// CHECK-INST: fcmla z0.d, p0/m, z1.d, z2.d, #90
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// CHECK-ENCODING: [0x20,0x20,0xc2,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 20 20 c2 64 <unknown>
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fcmla z29.h, p7/m, z30.h, z31.h, #180
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// CHECK-INST: fcmla z29.h, p7/m, z30.h, z31.h, #180
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// CHECK-ENCODING: [0xdd,0x5f,0x5f,0x64]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: dd 5f 5f 64 <unknown>
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fcmla z29.s, p7/m, z30.s, z31.s, #180
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// CHECK-INST: fcmla z29.s, p7/m, z30.s, z31.s, #180
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// CHECK-ENCODING: [0xdd,0x5f,0x9f,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: dd 5f 9f 64 <unknown>
|
||||
|
||||
fcmla z29.d, p7/m, z30.d, z31.d, #180
|
||||
// CHECK-INST: fcmla z29.d, p7/m, z30.d, z31.d, #180
|
||||
// CHECK-ENCODING: [0xdd,0x5f,0xdf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: dd 5f df 64 <unknown>
|
||||
|
||||
fcmla z31.h, p7/m, z31.h, z31.h, #270
|
||||
// CHECK-INST: fcmla z31.h, p7/m, z31.h, z31.h, #270
|
||||
// CHECK-ENCODING: [0xff,0x7f,0x5f,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 7f 5f 64 <unknown>
|
||||
|
||||
fcmla z31.s, p7/m, z31.s, z31.s, #270
|
||||
// CHECK-INST: fcmla z31.s, p7/m, z31.s, z31.s, #270
|
||||
// CHECK-ENCODING: [0xff,0x7f,0x9f,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 7f 9f 64 <unknown>
|
||||
|
||||
fcmla z31.d, p7/m, z31.d, z31.d, #270
|
||||
// CHECK-INST: fcmla z31.d, p7/m, z31.d, z31.d, #270
|
||||
// CHECK-ENCODING: [0xff,0x7f,0xdf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 7f df 64 <unknown>
|
||||
|
||||
fcmla z0.h, z0.h, z0.h[0], #0
|
||||
// CHECK-INST: fcmla z0.h, z0.h, z0.h[0], #0
|
||||
// CHECK-ENCODING: [0x00,0x10,0xa0,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 10 a0 64 <unknown>
|
||||
|
||||
fcmla z23.s, z13.s, z8.s[0], #270
|
||||
// CHECK-INST: fcmla z23.s, z13.s, z8.s[0], #270
|
||||
// CHECK-ENCODING: [0xb7,0x1d,0xe8,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: b7 1d e8 64 <unknown>
|
||||
|
||||
fcmla z31.h, z31.h, z7.h[3], #270
|
||||
// CHECK-INST: fcmla z31.h, z31.h, z7.h[3], #270
|
||||
// CHECK-ENCODING: [0xff,0x1f,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: ff 1f bf 64 <unknown>
|
||||
|
||||
fcmla z21.s, z10.s, z5.s[1], #90
|
||||
// CHECK-INST: fcmla z21.s, z10.s, z5.s[1], #90
|
||||
// CHECK-ENCODING: [0x55,0x15,0xf5,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 55 15 f5 64 <unknown>
|
||||
Loading…
Reference in New Issue