forked from OSchip/llvm-project
Revert rL363678 : AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics
There may or may not be additional work to handle this correctly on SI/CI. ........ Breaks EXPENSIVE_CHECKS buildbots - http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/78/ llvm-svn: 363797
This commit is contained in:
Simon Pilgrim
parent
e3cd19d330
commit
128ce93c60
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@ -1348,28 +1348,6 @@ def int_amdgcn_alignbyte : Intrinsic<[llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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// llvm.amdgcn.ds.gws.init(i32 bar_val, i32 resource_id)
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//
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// bar_val is the total number of waves that will wait on this
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// barrier, minus 1.
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def int_amdgcn_ds_gws_init :
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GCCBuiltin<"__builtin_amdgcn_ds_gws_init">,
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Intrinsic<[],
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[llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrWriteMem, IntrInaccessibleMemOnly], "",
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[SDNPMemOperand]
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>;
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// llvm.amdgcn.ds.gws.barrier(i32 vsrc0, i32 resource_id)
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// bar_val is the total number of waves that will wait on this
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// barrier, minus 1.
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def int_amdgcn_ds_gws_barrier :
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GCCBuiltin<"__builtin_amdgcn_ds_gws_barrier">,
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Intrinsic<[],
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[llvm_i32_ty, llvm_i32_ty],
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[IntrConvergent, IntrInaccessibleMemOnly], "",
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[SDNPMemOperand]
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>;
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// Copies the source value to the destination value, with the guarantee that
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// the source value is computed as if the entire program were executed in WQM.
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@ -218,9 +218,7 @@ private:
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void SelectFMAD_FMA(SDNode *N);
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void SelectATOMIC_CMP_SWAP(SDNode *N);
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void SelectDSAppendConsume(SDNode *N, unsigned IntrID);
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void SelectDS_GWS(SDNode *N, unsigned IntrID);
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void SelectINTRINSIC_W_CHAIN(SDNode *N);
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void SelectINTRINSIC_VOID(SDNode *N);
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protected:
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// Include the pieces autogenerated from the target description.
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@ -834,10 +832,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
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SelectINTRINSIC_W_CHAIN(N);
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return;
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}
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case ISD::INTRINSIC_VOID: {
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SelectINTRINSIC_VOID(N);
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return;
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}
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}
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SelectCode(N);
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@ -2040,73 +2034,6 @@ void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) {
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CurDAG->setNodeMemRefs(cast<MachineSDNode>(Selected), {MMO});
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}
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void AMDGPUDAGToDAGISel::SelectDS_GWS(SDNode *N, unsigned IntrID) {
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SDLoc SL(N);
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SDValue VSrc0 = N->getOperand(2);
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SDValue BaseOffset = N->getOperand(3);
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int ImmOffset = 0;
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SDNode *CopyToM0;
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MemIntrinsicSDNode *M = cast<MemIntrinsicSDNode>(N);
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MachineMemOperand *MMO = M->getMemOperand();
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// Don't worry if the offset ends up in a VGPR. Only one lane will have
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// effect, so SIFixSGPRCopies will validly insert readfirstlane.
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// The resource id offset is computed as (<isa opaque base> + M0[21:16] +
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// offset field) % 64. Some versions of the programming guide omit the m0
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// part, or claim it's from offset 0.
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if (ConstantSDNode *ConstOffset = dyn_cast<ConstantSDNode>(BaseOffset)) {
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// If we have a constant offset, try to use the default value for m0 as a
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// base to possibly avoid setting it up.
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CopyToM0 = glueCopyToM0(N, CurDAG->getTargetConstant(-1, SL, MVT::i32));
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ImmOffset = ConstOffset->getZExtValue() + 1;
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} else {
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if (CurDAG->isBaseWithConstantOffset(BaseOffset)) {
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ImmOffset = BaseOffset.getConstantOperandVal(1);
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BaseOffset = BaseOffset.getOperand(0);
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}
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// Prefer to do the shift in an SGPR since it should be possible to use m0
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// as the result directly. If it's already an SGPR, it will be eliminated
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// later.
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SDNode *SGPROffset
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= CurDAG->getMachineNode(AMDGPU::V_READFIRSTLANE_B32, SL, MVT::i32,
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BaseOffset);
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// Shift to offset in m0
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SDNode *M0Base
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= CurDAG->getMachineNode(AMDGPU::S_LSHL_B32, SL, MVT::i32,
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SDValue(SGPROffset, 0),
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CurDAG->getTargetConstant(16, SL, MVT::i32));
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CopyToM0 = glueCopyToM0(N, SDValue(M0Base, 0));
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}
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// The manual doesn't mention this, but it seems only v0 works.
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SDValue V0 = CurDAG->getRegister(AMDGPU::VGPR0, MVT::i32);
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SDValue CopyToV0 = CurDAG->getCopyToReg(
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SDValue(CopyToM0, 0), SL, V0, VSrc0,
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N->getOperand(N->getNumOperands() - 1));
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SDValue OffsetField = CurDAG->getTargetConstant(ImmOffset, SL, MVT::i32);
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// TODO: Can this just be removed from the instruction?
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SDValue GDS = CurDAG->getTargetConstant(1, SL, MVT::i1);
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unsigned Opc = IntrID == Intrinsic::amdgcn_ds_gws_init ?
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AMDGPU::DS_GWS_INIT : AMDGPU::DS_GWS_BARRIER;
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SDValue Ops[] = {
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V0,
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OffsetField,
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GDS,
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CopyToV0, // Chain
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CopyToV0.getValue(1) // Glue
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};
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SDNode *Selected = CurDAG->SelectNodeTo(N, Opc, N->getVTList(), Ops);
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CurDAG->setNodeMemRefs(cast<MachineSDNode>(Selected), {MMO});
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}
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void AMDGPUDAGToDAGISel::SelectINTRINSIC_W_CHAIN(SDNode *N) {
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unsigned IntrID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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switch (IntrID) {
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@ -2117,18 +2044,6 @@ void AMDGPUDAGToDAGISel::SelectINTRINSIC_W_CHAIN(SDNode *N) {
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SelectDSAppendConsume(N, IntrID);
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return;
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}
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}
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SelectCode(N);
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}
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void AMDGPUDAGToDAGISel::SelectINTRINSIC_VOID(SDNode *N) {
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unsigned IntrID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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switch (IntrID) {
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier:
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SelectDS_GWS(N, IntrID);
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return;
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default:
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break;
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}
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@ -467,15 +467,11 @@ defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
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defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
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defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
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let isConvergent = 1 in {
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def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init"> {
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let mayLoad = 0;
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}
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def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
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def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
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def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
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def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
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def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
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}
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def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
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def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
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@ -961,24 +961,6 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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return true;
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}
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier: {
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Info.opc = ISD::INTRINSIC_VOID;
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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Info.ptrVal =
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MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
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// This is an abstract access, but we need to specify a type and size.
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Info.memVT = MVT::i32;
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Info.size = 4;
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Info.align = 4;
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Info.flags = MachineMemOperand::MOStore;
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if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
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Info.flags = MachineMemOperand::MOLoad;
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return true;
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}
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default:
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return false;
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}
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@ -536,19 +536,15 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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// Put score on the source vgprs. If this is a store, just use those
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// specific register(s).
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if (TII->isDS(Inst) && (Inst.mayStore() || Inst.mayLoad())) {
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int AddrOpIdx =
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AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr);
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// All GDS operations must protect their address register (same as
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// export.)
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if (AddrOpIdx != -1) {
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setExpScore(&Inst, TII, TRI, MRI, AddrOpIdx, CurrScore);
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} else {
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assert(Inst.getOpcode() == AMDGPU::DS_APPEND ||
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Inst.getOpcode() == AMDGPU::DS_CONSUME ||
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Inst.getOpcode() == AMDGPU::DS_GWS_INIT ||
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Inst.getOpcode() == AMDGPU::DS_GWS_BARRIER);
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if (Inst.getOpcode() != AMDGPU::DS_APPEND &&
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Inst.getOpcode() != AMDGPU::DS_CONSUME) {
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setExpScore(
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&Inst, TII, TRI, MRI,
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AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::addr),
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CurrScore);
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}
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if (Inst.mayStore()) {
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if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
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AMDGPU::OpName::data0) != -1) {
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@ -1411,6 +1407,18 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
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ScoreBrackets.dump();
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});
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// Check to see if this is a GWS instruction. If so, and if this is CI or
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// VI, then the generated code sequence will include an S_WAITCNT 0.
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// TODO: Are these the only GWS instructions?
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if (Inst.getOpcode() == AMDGPU::DS_GWS_INIT ||
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Inst.getOpcode() == AMDGPU::DS_GWS_SEMA_V ||
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Inst.getOpcode() == AMDGPU::DS_GWS_SEMA_BR ||
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Inst.getOpcode() == AMDGPU::DS_GWS_SEMA_P ||
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Inst.getOpcode() == AMDGPU::DS_GWS_BARRIER) {
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// TODO: && context->target_info->GwsRequiresMemViolTest() ) {
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ScoreBrackets.applyWaitcnt(AMDGPU::Waitcnt::allZeroExceptVsCnt());
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}
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// TODO: Remove this work-around after fixing the scheduler and enable the
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// assert above.
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if (VCCZBugWorkAround) {
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@ -2547,8 +2547,7 @@ bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
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// given the typical code patterns.
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if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
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Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE ||
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Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
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Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
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Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP)
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return true;
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if (MI.isCall() || MI.isInlineAsm())
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@ -43,8 +43,7 @@ class AMDGPUPseudoSourceValue : public PseudoSourceValue {
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public:
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enum AMDGPUPSVKind : unsigned {
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PSVBuffer = PseudoSourceValue::TargetCustom,
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PSVImage,
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GWSResource
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PSVImage
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};
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protected:
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@ -88,30 +87,6 @@ public:
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}
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};
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class AMDGPUGWSResourcePseudoSourceValue final : public AMDGPUPseudoSourceValue {
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public:
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explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII)
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: AMDGPUPseudoSourceValue(GWSResource, TII) {}
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static bool classof(const PseudoSourceValue *V) {
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return V->kind() == GWSResource;
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}
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// These are inaccessible memory from IR.
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bool isAliased(const MachineFrameInfo *) const override {
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return false;
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}
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// These are inaccessible memory from IR.
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bool mayAlias(const MachineFrameInfo *) const override {
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return false;
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}
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void printCustom(raw_ostream &OS) const override {
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OS << "GWSResource";
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}
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};
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namespace yaml {
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struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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@ -213,7 +188,6 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
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std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
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DenseMap<const Value *,
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std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
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std::unique_ptr<const AMDGPUGWSResourcePseudoSourceValue> GWSResourcePSV;
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private:
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unsigned LDSWaveSpillSize = 0;
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@ -700,15 +674,6 @@ public:
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return PSV.first->second.get();
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}
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const AMDGPUGWSResourcePseudoSourceValue *getGWSPSV(const SIInstrInfo &TII) {
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if (!GWSResourcePSV) {
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GWSResourcePSV =
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llvm::make_unique<AMDGPUGWSResourcePseudoSourceValue>(TII);
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}
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return GWSResourcePSV.get();
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}
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unsigned getOccupancy() const {
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return Occupancy;
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}
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@ -1,103 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=VI %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=CI %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=SI %s
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---
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name: m0_gws_init0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GFX9-LABEL: name: m0_gws_init0
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; GFX9: liveins: $vgpr0
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; GFX9: $m0 = S_MOV_B32 -1
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; GFX9: S_NOP 0
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; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; VI-LABEL: name: m0_gws_init0
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; VI: liveins: $vgpr0
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; VI: $m0 = S_MOV_B32 -1
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; VI: S_NOP 0
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; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; CI-LABEL: name: m0_gws_init0
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; CI: liveins: $vgpr0
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; CI: $m0 = S_MOV_B32 -1
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; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; SI-LABEL: name: m0_gws_init0
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; SI: liveins: $vgpr0
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; SI: $m0 = S_MOV_B32 -1
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; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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...
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---
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name: m0_gws_init1
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tracksRegLiveness: true
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body: |
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bb.0:
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; GFX9-LABEL: name: m0_gws_init1
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; GFX9: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; GFX9: $m0 = S_MOV_B32 -1
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; GFX9: S_NOP 0
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; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; VI-LABEL: name: m0_gws_init1
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; VI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; VI: $m0 = S_MOV_B32 -1
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; VI: S_NOP 0
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; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; CI-LABEL: name: m0_gws_init1
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; CI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CI: $m0 = S_MOV_B32 -1
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; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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; SI-LABEL: name: m0_gws_init1
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; SI: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; SI: $m0 = S_MOV_B32 -1
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; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
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...
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# Test a typical situation where m0 needs to be set from a VGPR
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# through readfirstlane
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---
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name: m0_gws_readlane
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tracksRegLiveness: true
|
||||
body: |
|
||||
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX9-LABEL: name: m0_gws_readlane
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
|
||||
; GFX9: $m0 = S_MOV_B32 $sgpr0
|
||||
; GFX9: S_NOP 0
|
||||
; GFX9: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
; VI-LABEL: name: m0_gws_readlane
|
||||
; VI: liveins: $vgpr0, $vgpr1
|
||||
; VI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
|
||||
; VI: $m0 = S_MOV_B32 $sgpr0
|
||||
; VI: S_NOP 0
|
||||
; VI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
; CI-LABEL: name: m0_gws_readlane
|
||||
; CI: liveins: $vgpr0, $vgpr1
|
||||
; CI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
|
||||
; CI: $m0 = S_MOV_B32 $sgpr0
|
||||
; CI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
; SI-LABEL: name: m0_gws_readlane
|
||||
; SI: liveins: $vgpr0, $vgpr1
|
||||
; SI: $sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
|
||||
; SI: $m0 = S_MOV_B32 $sgpr0
|
||||
; SI: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
$sgpr0 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
|
||||
$m0 = S_MOV_B32 $sgpr0
|
||||
DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
|
||||
...
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-insert-skips -amdgpu-skip-threshold=1 -verify-machineinstrs %s -o - | FileCheck %s
|
||||
# Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0
|
||||
|
||||
---
|
||||
|
||||
name: skip_gws_init
|
||||
body: |
|
||||
; CHECK-LABEL: name: skip_gws_init
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: SI_MASK_BRANCH %bb.2, implicit $exec
|
||||
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
||||
; CHECK: DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
; CHECK: bb.2:
|
||||
; CHECK: S_ENDPGM 0
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
SI_MASK_BRANCH %bb.2, implicit $exec
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
||||
DS_GWS_INIT $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: skip_gws_barrier
|
||||
body: |
|
||||
; CHECK-LABEL: name: skip_gws_barrier
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: SI_MASK_BRANCH %bb.2, implicit $exec
|
||||
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
||||
; CHECK: DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
; CHECK: bb.2:
|
||||
; CHECK: S_ENDPGM 0
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
SI_MASK_BRANCH %bb.2, implicit $exec
|
||||
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
||||
DS_GWS_BARRIER $vgpr0, 0, 1, implicit $m0, implicit $exec
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
|
@ -1,179 +0,0 @@
|
|||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIPLUS %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIPLUS %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIPLUS %s
|
||||
|
||||
; Minimum offset
|
||||
; GCN-LABEL: {{^}}gws_barrier_offset0:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: s_mov_b32 m0, -1{{$}}
|
||||
; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 offset:1 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Maximum offset
|
||||
; GCN-LABEL: {{^}}gws_barrier_offset63:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: s_mov_b32 m0, -1{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 offset:64 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 63)
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Should be able to shift directly into m0
|
||||
; GCN-LABEL: {{^}}gws_barrier_sgpr_offset:
|
||||
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Variable offset in SGPR with constant add
|
||||
; GCN-LABEL: {{^}}gws_barrier_sgpr_offset_add1:
|
||||
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 offset:1 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
|
||||
%offset = add i32 %offset.base, 1
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gws_barrier_vgpr_offset:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_vgpr_offset(i32 %val) #0 {
|
||||
%vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %vgpr.offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Variable offset in VGPR with constant add
|
||||
; GCN-LABEL: {{^}}gws_barrier_vgpr_offset_add:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_barrier v0 offset:3 gds{{$}}
|
||||
define amdgpu_kernel void @gws_barrier_vgpr_offset_add(i32 %val) #0 {
|
||||
%vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%vgpr.offset = add i32 %vgpr.offset.base, 3
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %vgpr.offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
@lds = internal unnamed_addr addrspace(3) global i32 undef
|
||||
|
||||
; Check if m0 initialization is shared
|
||||
; GCN-LABEL: {{^}}gws_barrier_save_m0_barrier_constant_offset:
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN-NOT: s_mov_b32 m0
|
||||
define amdgpu_kernel void @gws_barrier_save_m0_barrier_constant_offset(i32 %val) #0 {
|
||||
store i32 1, i32 addrspace(3)* @lds
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 10)
|
||||
store i32 2, i32 addrspace(3)* @lds
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure this increments lgkmcnt
|
||||
; GCN-LABEL: {{^}}gws_barrier_lgkmcnt:
|
||||
; GCN: ds_gws_barrier v0 offset:1 gds{{$}}
|
||||
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: s_setpc_b64
|
||||
define void @gws_barrier_lgkmcnt(i32 %val) {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Does not imply memory fence on its own
|
||||
; GCN-LABEL: {{^}}gws_barrier_wait_before:
|
||||
; GCN: store_dword
|
||||
; CIPLUS-NOT: s_waitcnt
|
||||
; GCN: ds_gws_barrier v0 offset:8 gds
|
||||
define amdgpu_kernel void @gws_barrier_wait_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
|
||||
store i32 0, i32 addrspace(1)* %ptr
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gws_barrier_wait_after:
|
||||
; GCN: ds_gws_barrier v0 offset:8 gds
|
||||
; GCN-NEXT: s_waitcnt expcnt(0){{$}}
|
||||
; GCN-NEXT: load_dword
|
||||
define amdgpu_kernel void @gws_barrier_wait_after(i32 %val, i32 addrspace(1)* %ptr) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
%load = load volatile i32, i32 addrspace(1)* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Does not imply memory fence on its own
|
||||
; GCN-LABEL: {{^}}gws_barrier_fence_before:
|
||||
; GCN: store_dword
|
||||
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; GCN: ds_gws_barrier v0 offset:8 gds
|
||||
define amdgpu_kernel void @gws_barrier_fence_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
|
||||
store i32 0, i32 addrspace(1)* %ptr
|
||||
fence release
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gws_barrier_fence_after:
|
||||
; GCN: ds_gws_barrier v0 offset:8 gds
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: load_dword
|
||||
define amdgpu_kernel void @gws_barrier_fence_after(i32 %val, i32 addrspace(1)* %ptr) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
fence release
|
||||
%load = load volatile i32, i32 addrspace(1)* %ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Should a wait be inserted here, or is an explicit fence needed?
|
||||
; GCN-LABEL: {{^}}gws_init_barrier:
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN: ds_gws_init v0 offset:8 gds
|
||||
; GCN-NEXT: ds_gws_barrier v0 offset:8 gds
|
||||
define amdgpu_kernel void @gws_init_barrier(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Why vmcnt, not expcnt?
|
||||
; GCN-LABEL: {{^}}gws_init_fence_barrier:
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN: ds_gws_init v0 offset:8 gds
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: ds_gws_barrier v0 offset:8 gds
|
||||
define amdgpu_kernel void @gws_init_fence_barrier(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
|
||||
fence release
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #1
|
||||
declare void @llvm.amdgcn.ds.gws.init(i32, i32) #2
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #3
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { convergent inaccessiblememonly nounwind }
|
||||
attributes #2 = { convergent inaccessiblememonly nounwind writeonly }
|
||||
attributes #3 = { nounwind readnone speculatable }
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
|
||||
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s
|
||||
|
||||
; Minimum offset
|
||||
; GCN-LABEL: {{^}}gws_init_offset0:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: s_mov_b32 m0, -1{{$}}
|
||||
; GCN: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 offset:1 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_offset0(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Maximum offset
|
||||
; GCN-LABEL: {{^}}gws_init_offset63:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: s_mov_b32 m0, -1{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 offset:64 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_offset63(i32 %val) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 63)
|
||||
ret void
|
||||
}
|
||||
|
||||
; FIXME: Should be able to shift directly into m0
|
||||
; GCN-LABEL: {{^}}gws_init_sgpr_offset:
|
||||
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_sgpr_offset(i32 %val, i32 %offset) #0 {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Variable offset in SGPR with constant add
|
||||
; GCN-LABEL: {{^}}gws_init_sgpr_offset_add1:
|
||||
; GCN-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 offset:1 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
|
||||
%offset = add i32 %offset.base, 1
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gws_init_vgpr_offset:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_vgpr_offset(i32 %val) #0 {
|
||||
%vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Variable offset in VGPR with constant add
|
||||
; GCN-LABEL: {{^}}gws_init_vgpr_offset_add:
|
||||
; GCN-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
|
||||
; GCN-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
|
||||
; GCN-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
|
||||
; GCN-DAG: s_mov_b32 m0, [[SHL]]{{$}}
|
||||
; GCN-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
|
||||
; GCN: ds_gws_init v0 offset:3 gds{{$}}
|
||||
define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
|
||||
%vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%vgpr.offset = add i32 %vgpr.offset.base, 3
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %vgpr.offset)
|
||||
ret void
|
||||
}
|
||||
|
||||
@lds = internal unnamed_addr addrspace(3) global i32 undef
|
||||
|
||||
; Check if m0 initialization is shared.
|
||||
; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset:
|
||||
; GCN: s_mov_b32 m0, -1
|
||||
; GCN-NOT: s_mov_b32 m0
|
||||
define amdgpu_kernel void @gws_init_save_m0_init_constant_offset(i32 %val) #0 {
|
||||
store i32 1, i32 addrspace(3)* @lds
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 10)
|
||||
store i32 2, i32 addrspace(3)* @lds
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}gws_init_lgkmcnt:
|
||||
; GCN: ds_gws_init v0 offset:1 gds{{$}}
|
||||
; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: s_setpc_b64
|
||||
define void @gws_init_lgkmcnt(i32 %val) {
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Does not imply memory fence on its own
|
||||
; GCN-LABEL: {{^}}gws_init_wait_before:
|
||||
; GCN: store_dword
|
||||
; CIPLUS-NOT: s_waitcnt
|
||||
; GCN: ds_gws_init v0 offset:8 gds
|
||||
define amdgpu_kernel void @gws_init_wait_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
|
||||
store i32 0, i32 addrspace(1)* %ptr
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.ds.gws.init(i32, i32) #1
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { convergent inaccessiblememonly nounwind writeonly }
|
||||
attributes #2 = { nounwind readnone speculatable }
|
||||
|
|
@ -6,8 +6,6 @@
|
|||
declare void @nonconvergent_func() #0
|
||||
declare void @convergent_func() #1
|
||||
declare void @llvm.amdgcn.s.barrier() #1
|
||||
declare void @llvm.amdgcn.ds.gws.init(i32, i32) #2
|
||||
declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #2
|
||||
|
||||
; barrier shouldn't be duplicated.
|
||||
|
||||
|
|
@ -102,52 +100,6 @@ call:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}taildup_gws_init:
|
||||
; GCN: ds_gws_init
|
||||
; GCN-NOT: ds_gws_init
|
||||
define amdgpu_kernel void @taildup_gws_init(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond, i32 %val, i32 %offset) #0 {
|
||||
entry:
|
||||
br i1 %cond, label %bb1, label %bb2
|
||||
|
||||
bb1:
|
||||
store i32 0, i32 addrspace(1)* %a
|
||||
br label %call
|
||||
|
||||
bb2:
|
||||
store i32 1, i32 addrspace(1)* %a
|
||||
br label %call
|
||||
|
||||
call:
|
||||
call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 %offset)
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}taildup_gws_barrier:
|
||||
; GCN: ds_gws_barrier
|
||||
; GCN-NOT: ds_gws_barrier
|
||||
define amdgpu_kernel void @taildup_gws_barrier(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i1 %cond, i32 %val, i32 %offset) #0 {
|
||||
entry:
|
||||
br i1 %cond, label %bb1, label %bb2
|
||||
|
||||
bb1:
|
||||
store i32 0, i32 addrspace(1)* %a
|
||||
br label %call
|
||||
|
||||
bb2:
|
||||
store i32 1, i32 addrspace(1)* %a
|
||||
br label %call
|
||||
|
||||
call:
|
||||
call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind convergent }
|
||||
attributes #2 = { convergent inaccessiblememonly nounwind }
|
||||
|
|
|
|||
Loading…
Reference in New Issue