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ARM Unwind syntax 

This patch fixes the bad argument that GAS accepted but the IAS didn't,
ie. {#0x20}, moving it to {0x20} which both accept. It also makes the
ARMv7+ save/restore correct by using VFP instructions rather than old
co-processor ones.

Fixes PR20529.

llvm-svn: 217585
This commit is contained in:
Renato Golin 2014-09-11 12:57:02 +00:00
parent e579c76bd5
commit 128485ba47
2 changed files with 30 additions and 6 deletions
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18
libcxxabi/src/Unwind/UnwindRegistersRestore.S
View File

@ -347,7 +347,11 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFL
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instruction using the corresponding coprocessor mnemonic.
ldc p11, cr0, [r0], {#0x20} @ fldmiad r0, {d0-d15}
#if __ARM_ARCH < 7
ldc p11, cr0, [r0], {0x20} @ fldmiad r0, {d0-d15}
#else
vldmia r0, {d0-d15}
#endif
mov pc, lr
@
@ -358,7 +362,11 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFL
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFLDMXEPy)
ldc p11, cr0, [r0], {#0x21} @ fldmiax r0, {d0-d15}
#if __ARM_ARCH < 7
ldc p11, cr0, [r0], {0x21} @ fldmiax r0, {d0-d15}
#else
vldmia r0, {d0-d15} @ fldmiax is deprecated in ARMv7+ and now behaves like vldmia
#endif
mov pc, lr
@
@ -369,7 +377,11 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm19restoreVFPWithFL
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm12restoreVFPv3EPy)
ldcl p11, cr0, [r0], {#0x20} @ vldm r0, {d16-d31}
#if __ARM_ARCH < 7
ldcl p11, cr0, [r0], {0x20} @ vldm r0, {d16-d31}
#else
vldmia r0, {d16-d31}
#endif
mov pc, lr
@

18
libcxxabi/src/Unwind/UnwindRegistersSave.S
View File

@ -318,7 +318,11 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext)
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMDEPy)
stc p11, cr0, [r0], {#0x20} @ fstmiad r0, {d0-d15}
#if __ARM_ARCH < 7
stc p11, cr0, [r0], {0x20} @ fstmiad r0, {d0-d15}
#else
vstmia r0, {d0-d15}
#endif
mov pc, lr
@
@ -329,7 +333,11 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMD
@
.p2align 2
DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm16saveVFPWithFSTMXEPy)
stc p11, cr0, [r0], {#0x21} @ fstmiax r0, {d0-d15}
#if __ARM_ARCH < 7
stc p11, cr0, [r0], {0x21} @ fstmiax r0, {d0-d15}
#else
vstmia r0, {d0-d15} @ fstmiax is deprecated in ARMv7+ and now behaves like vstmia
#endif
mov pc, lr
@
@ -347,7 +355,11 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_arm9saveVFPv3EPy)
@ these registers implies they are, actually, available on the target, so
@ it's ok to execute.
@ So, generate the instructions using the corresponding coprocessor mnemonic.
stcl p11, cr0, [r0], {#0x20} @ vldm r0, {d16-d31}
#if __ARM_ARCH < 7
stcl p11, cr0, [r0], {0x20} @ vstm r0, {d16-d31}
#else
vstmia r0, {d16-d31}
#endif
mov pc, lr
@