From 121caf631372cf44f2bb1bdfd29bcf1c76f2073b Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Wed, 26 Feb 2014 20:20:30 +0000
Subject: [PATCH] Fix the aggressive anti-dep breaker's subregister definition
 handling

The aggressive anti-dependency breaker scans instructions, bottom-up, within the
scheduling region in order to find opportunities where register renaming can
be used to break anti-dependencies.

Unfortunately, the aggressive anti-dep breaker was treating a register definition
as defining all of that register's aliases (including super registers). This behavior
is incorrect when the super register is live and there are other definitions of
subregisters of the super register.

For example, given the following sequence:

%CR2EQ<def> = CROR %CR3UN, %CR3UN<kill>
%CR2GT<def> = IMPLICIT_DEF
%X4<def> = MFOCRF8 %CR2

the analysis of the first subregister definition would work as expected:
Anti:   %CR2GT<def> = IMPLICIT_DEF
        Def Groups: CR2GT=g194->g0(via CR2)
        Antidep reg: CR2GT (zero group)
        Use Groups:

but the analysis of the second one would not:
Anti:   %CR2EQ<def> = CROR %CR3UN, %CR3UN<kill>
        Def Groups: CR2EQ=g195
        Antidep reg: CR2EQ
        Rename Candidates for Group g195: ...

because, when processing the %CR2GT<def>, we'd mark all super registers of
%CR2GT (%CR2 in this case) as defined. As a result, when processing
%CR2EQ<def>, %CR2 no longer appears to be live, and %CR2EQ<def>'s group is not
%unioned with the %CR2 group.

I don't have an in-tree test case for this yet (and even if I did, I don't have
a small one).

llvm-svn: 202294
---
 llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 2ee776711587..25c438c9615a 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -403,8 +403,18 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
       continue;
 
     // Update def for Reg and aliases.
-    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
+    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
+      // We need to be careful here not to define already-live super registers.
+      // If the super register is already live, then this definition is not
+      // a definition of the whole super register (just a partial insertion
+      // into it). Earlier subregister definitions (which we've not yet visited
+      // because we're iterating bottom-up) need to be linked to the same group
+      // as this definition.
+      if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
+        continue;
+
       DefIndices[*AI] = Count;
+    }
   }
 }